📄 test_kc.uc
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RF:5:IN:0:REG:1 = B:27 STAGE:-1 VAR: tmp#9 DATATYPE: INT,
// IN:COMM_SCHED_0: ( tmp#9 ) = COMMUCPERM( perm_b == UCRF_0[3], sum == UNITRF_0_1[1] )
// OUT:COMM_SCHED_0: COMMUCPERM => ( tmp#9 == UNITRF_0_4[1] )
DEAD_REGS: { };
instr: 17
MC: OP: NONE LINE:-1,
U2: OP: IADD32 LINE:47 STAGE:-1, // D:\working\im_apps\test\test_kc.i:47
B:17 = RF:9:OUT:0:REG:1 VAR: sum DATATYPE: INT,
U2:IN:1 = B:17 VAR: sum DATATYPE: INT,
B:16 = RF:5:OUT:0:REG:1 VAR: tmp#9 DATATYPE: INT,
U2:IN:0 = B:16 VAR: tmp#9 DATATYPE: INT,
// IN:ADDER_2: ( sum ) = IADD32( sum == UNITRF_1_3[1], tmp#9 == UNITRF_0_4[1] )
DEAD_REGS: { };
instr: 18
MC: OP: NONE LINE:-1,
B:31 = U2:OUT:0 INSTR_LOG:2|sum#||0 VAR: sum DATATYPE: INT,
RF:2:IN:0:REG:1 = B:31 STAGE:-1 VAR: sum DATATYPE: INT,
RF:8:IN:0:REG:1 = B:31 STAGE:-1 VAR: sum DATATYPE: INT,
// OUT:ADDER_2: IADD32 => ( sum == UNITRF_0_1[1], sum == UNITRF_1_2[1] )
DEAD_REGS: { };
instr: 19
MC: OP: NONE LINE:-1 UCRF_RD:4,
U7: OP: COMMUCPERM LINE:49 STAGE:-1, // D:\working\im_apps\test\test_kc.i:49
B:8 = RF:2:OUT:0:REG:1 VAR: sum DATATYPE: INT,
U7:IN:0 = B:8 VAR: sum DATATYPE: INT,
B:27 = U7:OUT:0 INSTR_LOG:1|tmp#10#||0 VAR: tmp#10 DATATYPE: INT,
RF:4:IN:0:REG:1 = B:27 STAGE:-1 VAR: tmp#10 DATATYPE: INT,
// IN:COMM_SCHED_0: ( tmp#10 ) = COMMUCPERM( perm_c == UCRF_0[4], sum == UNITRF_0_1[1] )
// OUT:COMM_SCHED_0: COMMUCPERM => ( tmp#10 == UNITRF_0_3[1] )
DEAD_REGS: { };
instr: 20
MC: OP: NONE LINE:-1,
U1: OP: IADD32 LINE:49 STAGE:-1, // D:\working\im_apps\test\test_kc.i:49
B:15 = RF:8:OUT:0:REG:1 VAR: sum DATATYPE: INT,
U1:IN:1 = B:15 VAR: sum DATATYPE: INT,
B:14 = RF:4:OUT:0:REG:1 VAR: tmp#10 DATATYPE: INT,
U1:IN:0 = B:14 VAR: tmp#10 DATATYPE: INT,
// IN:ADDER_1: ( sum ) = IADD32( sum == UNITRF_1_2[1], tmp#10 == UNITRF_0_3[1] )
DEAD_REGS: { };
instr: 21
MC: OP: NONE LINE:-1,
B:30 = U1:OUT:0 INSTR_LOG:2|sum#||0 VAR: sum DATATYPE: INT,
RF:2:IN:0:REG:1 = B:30 STAGE:-1 VAR: sum DATATYPE: INT,
// OUT:ADDER_1: IADD32 => ( sum == UNITRF_0_1[1] )
DEAD_REGS: { };
instr: 22
MC: OP: NONE LINE:-1 UCRF_RD:-1 COMM_SRC_IDX:0,
U7: OP: COMMUCDATA LINE:52 STAGE:-1, // D:\working\im_apps\test\test_kc.i:52
B:8 = RF:2:OUT:0:REG:1 VAR: sum DATATYPE: INT,
U7:IN:0 = B:8 VAR: sum DATATYPE: INT,
// IN:COMM_SCHED_0: ( dummy ) = COMMUCDATA( sum == UNITRF_0_1[1] )
DEAD_REGS: { };
instr: 23
MC: OP: NONE LINE:-1 UCRF_WR:1 STAGES:-1 END:,
// OUT:COMM_SCHED_0: COMM_WR_UCR => ( uc_sum == UCRF_0[1] )
DEAD_REGS: { };
// Opcounts by block
// Block 0 (7 total cycles, 6 total ops)
// SELECT: 1
// NSELECT: 3
// COMMUCDATA: 1
// IEQ32: 1
//
// Block 1 (6 total cycles, 2 total ops)
// IADD32: 2
//
// Block 2 (11 total cycles, 7 total ops)
// COMMUCDATA: 1
// COMMUCPERM: 3
// IADD32: 3
//
// Register file references by block
// Block ID: CC reads, CC writes, RF reads, RF writes, SP reads, SP writes
// Block 0: 4 1 8 6 0 0
// U0: ( ADDER_0 ) : 1/7 ; 14.3%
// U1: ( ADDER_1 ) : 0/7 ; 0.0%
// U2: ( ADDER_2 ) : 1/7 ; 14.3%
// U3: ( MULTIPLIER_0 ) : 1/7 ; 14.3%
// U4: ( MULTIPLIER_1 ) : 1/7 ; 14.3%
// U5: ( DIVIDER_0 ) : 1/7 ; 14.3%
// U6: ( SP_SIM_FU_0 ) : 0/7 ; 0.0%
// U7: ( COMM_0 ) : 1/7 ; 14.3%
// U8: ( JUKEBOX_0 ) : 0/7 ; 0.0%
// U9: ( VALID_0 ) : 0/7 ; 0.0%
// Block 1: 0 0 4 5 0 0
// U0: ( ADDER_0 ) : 1/6 ; 16.7%
// U1: ( ADDER_1 ) : 1/6 ; 16.7%
// U2: ( ADDER_2 ) : 0/6 ; 0.0%
// U3: ( MULTIPLIER_0 ) : 0/6 ; 0.0%
// U4: ( MULTIPLIER_1 ) : 0/6 ; 0.0%
// U5: ( DIVIDER_0 ) : 0/6 ; 0.0%
// U6: ( SP_SIM_FU_0 ) : 0/6 ; 0.0%
// U7: ( COMM_0 ) : 0/6 ; 0.0%
// U8: ( JUKEBOX_0 ) : 0/6 ; 0.0%
// U9: ( VALID_0 ) : 0/6 ; 0.0%
// Block 2: 0 0 10 8 0 0
// U0: ( ADDER_0 ) : 1/11 ; 9.1%
// U1: ( ADDER_1 ) : 1/11 ; 9.1%
// U2: ( ADDER_2 ) : 1/11 ; 9.1%
// U3: ( MULTIPLIER_0 ) : 0/11 ; 0.0%
// U4: ( MULTIPLIER_1 ) : 0/11 ; 0.0%
// U5: ( DIVIDER_0 ) : 0/11 ; 0.0%
// U6: ( SP_SIM_FU_0 ) : 0/11 ; 0.0%
// U7: ( COMM_0 ) : 4/11 ; 36.4%
// U8: ( JUKEBOX_0 ) : 0/11 ; 0.0%
// U9: ( VALID_0 ) : 0/11 ; 0.0%
// maximum register allocation:
// idx: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
// max: 256 32 2 16 16 16 16 16 16 16 16 16 32 32 32 32 16 16
// use: 0 5 2 1 2 2 2 2 1 2 2 2 1 1 2 1 1 1
// idx: 18 19 20 21 22 23 24 25 26 27 28 29 30
// max: 16 16 16 16 16 1 1 1 1 1 1 1 1
// use: 1 1 2 1 1 0 0 0 0 0 0 0 0
// rf/functional unit mapping:
// ( 0) 0: SP_SC0 ( 1) -1: COMM_0 ( 2) -1: MC0 ( 3) 1: SP_SC0 ( 4) 2: COMM_0
// ( 5) 3: ADDER0 ( 6) 4: ADDER1 ( 7) 5: ADDER2 ( 8) 6: DIVID0 ( 9) 7: ADDER0
// (10) 8: ADDER1 (11) 9: ADDER2 (12) 10: MULTI0 (13) 11: MULTI1 (14) 12: MULTI0
// (15) 13: MULTI1 (16) 14: DIVID0 (17) 15: COMM_0 (18) 16: SP_SC0 (19) 17: SP_SC0
// (20) 18: JUKEB0 (21) 19: JUKEB0 (22) 20: VALID0 (23) 21: INOUT0 (24) 22: INOUT1
// (25) 23: INOUT2 (26) 24: INOUT3 (27) 25: INOUT4 (28) 26: INOUT5 (29) 27: INOUT6
// (30) 28: INOUT7
//------------------------------------------------------------
// BLOCK: 0
//------------------------------------------------------------
// Ideal communication: (write from ---^ to)
// ADD0 ADD1 ADD2 MUL0 MUL1 DIV0 INO0 INO1 INO2 INO3 INO4 INO5 INO6 INO7 SP_0 SP_0 COM0 MC0 JUK0 VAL0
// ADD0 0.2 0.2 0.2 0.1 0.1 0.1 . . . . . . . . . . 0.1 . 0.0 0.0
// ADD1 0.2 0.2 0.2 0.1 0.1 0.1 . . . . . . . . . . 0.1 . 0.0 0.0
// ADD2 0.2 0.2 0.2 0.1 0.1 0.1 . . . . . . . . . . 0.1 . 0.0 0.0
// MUL0 0.0 0.0 0.0 0.0 0.0 0.0 . . . . . . . . . . 0.0 . 0.0 0.0
// MUL1 0.0 0.0 0.0 0.0 0.0 0.0 . . . . . . . . . . 0.0 . 0.0 0.0
// DIV0 0.0 0.0 0.0 0.0 0.0 0.0 . . . . . . . . . . 0.0 . 0.0 0.0
// INO0 . . . . . . . . . . . . . . . . . . . .
// INO1 . . . . . . . . . . . . . . . . . . . .
// INO2 . . . . . . . . . . . . . . . . . . . .
// INO3 . . . . . . . . . . . . . . . . . . . .
// INO4 . . . . . . . . . . . . . . . . . . . .
// INO5 . . . . . . . . . . . . . . . . . . . .
// INO6 . . . . . . . . . . . . . . . . . . . .
// INO7 . . . . . . . . . . . . . . . . . . . .
// SP_0 . . . . . . . . . . . . . . . . . . . .
// SP_0 . . . . . . . . . . . . . . . . . . . .
// COM0 1.0 1.0 1.0 1.0 1.0 1.0 . . . . . . . . . . 1.0 . 0.0 0.0
// MC0 . . . . . . . . . . . . . . . . . 1.0 . .
// JUK0 0.0 0.0 0.0 . . . . . . . . . . . . . 0.0 . . .
// VAL0 0.0 0.0 0.0 . . . . . . . . . . . . . 0.0 . . .
// Real communication: (write from ---^ to)
// ADD0 ADD1 ADD2 MUL0 MUL1 DIV0 INO0 INO1 INO2 INO3 INO4 INO5 INO6 INO7 SP_0 SP_0 COM0 MC0 JUK0 VAL0
// ADD0 . . . 1.0 . . . . . . . . . . . . . . . .
// ADD1 . . . . . . . . . . . . . . . . . . . .
// ADD2 2.0 . . . . . . . . . . . . . . . 1.0 . . .
// MUL0 . . 1.0 . . . . . . . . . . . . . . . . .
// MUL1 1.0 . . . . . . . . . . . . . . . . . . .
// DIV0 1.0 . . . . . . . . . . . . . . . . . . .
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