test_kc.uc

H.264完整的C语言代码和DCT的代码

// microassembly program:  D:\working\im_apps\test\test_kc.i
// machine description:    gold8.md
// KERNELDEF: instrs: 24 params: i 0 i 1 o 2 u 1 blocks: 3 7 2  6 1  11 -1  SWP_block_depth: 3 -1 0 -1 func_name: addAndSum block_io_counts: 3 3 0 0 0 0 1 1 1 1 0 0 0 0 
PARAMS: SCHED_METHOD: COS UC_BITS: 497
         NUM_INPUT_STREAMS: 2 NUM_OUTPUT_STREAMS: 1

// RESULTS: -rs 0, -rf 0
//   block: 0 best: 5 achieved: 7 (lines: 1-31, instrs: 0-6)
//   block: 1 best: 6 achieved: 6 (lines: 32-42, instrs: 7-12)
//   block: 2 best: 11 achieved: 11 (lines: 43-52, instrs: 13-23)

instr: 0
    MC: OP: UC_DATA_IN LINE:27 IMM:0x67452301 UCRF_WR:2 STAGES:-1,
    // OUT:MC_0: UC_DATA_IN => ( perm_a == UCRF_0[2] )
    DEAD_REGS: {  };
instr: 1
    MC: OP: UC_DATA_IN LINE:28 IMM:0x44660022 UCRF_WR:3 STAGES:-1,
    // OUT:MC_0: UC_DATA_IN => ( perm_b == UCRF_0[3] )
    DEAD_REGS: {  };
instr: 2
    MC: OP: CHK_EOS LINE:31 STR_ID:0,
    DEAD_REGS: {  };
instr: 3
    MC: OP: NONE LINE:-1 UCONDRF_WR:1 STAGES:-1,
    U5: OP: SELECT LINE:-1 STAGE:-1, // D:\working\im_apps\test\test_kc.i:-1
    U4: OP: NSELECT LINE:-1 STAGE:-1, // D:\working\im_apps\test\test_kc.i:-1
    B:39 = RF:18:OUT:2:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U5:IN:2 = B:39 VAR: hw_const#0 DATATYPE: ANYINT,
    B:11 = RF:14:OUT:0:REG:0 VAR: cluster#id DATATYPE: ANYINT,
    U5:IN:1 = B:11 VAR: cluster#id DATATYPE: ANYINT,
    B:28 = U5:OUT:0 INSTR_LOG:1|cluster#id#||0 VAR: cluster#id DATATYPE: ANYINT,
    RF:3:IN:0:REG:1 = B:28 STAGE:-1 VAR: cluster#id DATATYPE: ANYINT,
    B:44 = RF:18:OUT:7:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U4:IN:2 = B:44 VAR: hw_const#0 DATATYPE: ANYINT,
    B:20 = RF:11:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U4:IN:0 = B:20 VAR: hw_const#0 DATATYPE: ANYINT,
    B:35 = U4:OUT:1 INSTR_LOG:1|const#0#||1 VAR: const#0 DATATYPE: ANYINT,
    RF:7:IN:0:REG:1 = B:35 STAGE:-1 VAR: const#0 DATATYPE: ANYINT,
    // OUT:MC_0: CHK_EOS => ( tmp#6 == UCONDRF_0[1] )
    //  IN:DIVIDER_0: ( cluster#id ) = SELECT( hw_const#0 == CCRF_0[0], cluster#id == UNITRF_CID_0[0] )
    // OUT:DIVIDER_0: SELECT => ( cluster#id == UNITRF_0_2[1] )
    //  IN:MULTIPLIER_1: ( const#0 ) = NSELECT( hw_const#0 == CCRF_0[0], hw_const#0 == MULRF_0_1[0] )
    // OUT:MULTIPLIER_1: NSELECT => ( const#0 == UNITRF_1_1[1] )
    DEAD_REGS: {  };
instr: 4
    MC: OP: NLOOP LINE:31 UCRF_RD:1 UCONDRF_RD:1 BR_OFF:7 LAST_STAGE:0,
    U7: OP: COMMUCDATA LINE:24 STAGE:-1, // D:\working\im_apps\test\test_kc.i:24
    U0: OP: IEQ32 LINE:26 STAGE:-1, // D:\working\im_apps\test\test_kc.i:26
    B:9 = RF:15:OUT:0:REG:0 VAR: hw_mctrl#id DATATYPE: ANYINT,
    U7:IN:1 = B:9 VAR: hw_mctrl#id DATATYPE: ANYINT,
    B:27 = U7:OUT:0 INSTR_LOG:1|sum#||0 VAR: sum DATATYPE: INT,
    RF:12:IN:0:REG:1 = B:27 STAGE:-1 VAR: sum DATATYPE: INT,
    B:12 = RF:3:OUT:0:REG:1 VAR: cluster#id DATATYPE: ANYINT,
    U0:IN:0 = B:12 VAR: cluster#id DATATYPE: ANYINT,
    B:13 = RF:7:OUT:0:REG:1 VAR: const#0 DATATYPE: ANYINT,
    U0:IN:1 = B:13 VAR: const#0 DATATYPE: ANYINT,
    B:45 = U0:OUT:0 INSTR_LOG:1|tmp#4#||0 VAR: tmp#4 DATATYPE: CC,
    RF:18:IN:0:REG:1 = B:45 STAGE:-1 VAR: tmp#4 DATATYPE: CC,
    //  IN:MC_0: ( ) = NLOOP( tmp#6 == UCONDRF_0[1] )
    //  IN:COMM_SCHED_0: ( sum ) = COMMUCDATA( hw_mctrl#id == PERMRF_0[0], uc_sum == UCRF_0[1] )
    // OUT:COMM_SCHED_0: COMMUCDATA => ( sum == MULRF_1_0[1] )
    //  IN:ADDER_0: ( tmp#4 ) = IEQ32( cluster#id == UNITRF_0_2[1], const#0 == UNITRF_1_1[1] )
    // OUT:ADDER_0: IEQ32 => ( tmp#4 == CCRF_0[1] )
    DEAD_REGS: {  };
instr: 5
    MC: OP: UC_DATA_IN LINE:29 IMM:0x4444 UCRF_WR:4 STAGES:-1,
    U3: OP: NSELECT LINE:26 STAGE:-1, // D:\working\im_apps\test\test_kc.i:26
    B:43 = RF:18:OUT:6:REG:1 VAR: tmp#4 DATATYPE: CC,
    U3:IN:2 = B:43 VAR: tmp#4 DATATYPE: CC,
    B:19 = RF:12:OUT:0:REG:1 VAR: sum DATATYPE: INT,
    U3:IN:1 = B:19 VAR: sum DATATYPE: INT,
    B:18 = RF:10:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U3:IN:0 = B:18 VAR: hw_const#0 DATATYPE: ANYINT,
    B:33 = U3:OUT:1 INSTR_LOG:1|tmp#5#||1 VAR: tmp#5 DATATYPE: INT,
    RF:5:IN:0:REG:1 = B:33 STAGE:-1 VAR: tmp#5 DATATYPE: INT,
    // OUT:MC_0: UC_DATA_IN => ( perm_c == UCRF_0[4] )
    //  IN:MULTIPLIER_0: ( tmp#5 ) = NSELECT( tmp#4 == CCRF_0[1], sum == MULRF_1_0[1], hw_const#0 == MULRF_0_0[0] )
    // OUT:MULTIPLIER_0: NSELECT => ( tmp#5 == UNITRF_0_4[1] )
    DEAD_REGS: {  };
instr: 6
    MC: OP: NONE LINE:-1,
    U2: OP: NSELECT LINE:26 STAGE:-1, // D:\working\im_apps\test\test_kc.i:26
    B:42 = RF:18:OUT:5:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U2:IN:2 = B:42 VAR: hw_const#0 DATATYPE: ANYINT,
    B:16 = RF:5:OUT:0:REG:1 VAR: tmp#5 DATATYPE: INT,
    U2:IN:0 = B:16 VAR: tmp#5 DATATYPE: INT,
    B:31 = U2:OUT:0 INSTR_LOG:1|sum#||0 VAR: sum DATATYPE: INT,
    RF:2:IN:0:REG:1 = B:31 STAGE:-1 VAR: sum DATATYPE: INT,
    RF:3:IN:0:REG:1 = B:31 STAGE:-1 VAR: sum DATATYPE: INT,
    //  IN:ADDER_2: ( sum ) = NSELECT( hw_const#0 == CCRF_0[0], tmp#5 == UNITRF_0_4[1] )
    // OUT:ADDER_2: NSELECT => ( sum == UNITRF_0_1[1], sum == UNITRF_0_2[1] )
    DEAD_REGS: {  };
instr: 7
    MC: OP: NONE LINE:-1,
    B:22 = IN:0 STAGE:-1 LINE:34 VAR: a1 DATATYPE: INT,
    RF:4:IN:0:REG:1 = B:22 STAGE:-1 VAR: a1 DATATYPE: INT,
    // OUT:INOUT_0: DATA_IN => ( a1 == UNITRF_0_3[1] )
    DEAD_REGS: {  };
instr: 8
    MC: OP: CHK_EOS LINE:42 STR_ID:0,
    B:23 = IN:1 STAGE:-1 LINE:35 VAR: b1 DATATYPE: INT,
    RF:8:IN:0:REG:1 = B:23 STAGE:-1 VAR: b1 DATATYPE: INT,
    // OUT:INOUT_1: DATA_IN => ( b1 == UNITRF_1_2[1] )
    DEAD_REGS: {  };
instr: 9
    MC: OP: NONE LINE:-1 UCONDRF_WR:1 STAGES:-1,
    U1: OP: IADD32 LINE:37 STAGE:-1, // D:\working\im_apps\test\test_kc.i:37
    B:14 = RF:4:OUT:0:REG:1 VAR: a1 DATATYPE: INT,
    U1:IN:0 = B:14 VAR: a1 DATATYPE: INT,
    B:15 = RF:8:OUT:0:REG:1 VAR: b1 DATATYPE: INT,
    U1:IN:1 = B:15 VAR: b1 DATATYPE: INT,
    // OUT:MC_0: CHK_EOS => ( tmp#7 == UCONDRF_0[1] )
    //  IN:ADDER_1: ( c1 ) = IADD32( a1 == UNITRF_0_3[1], b1 == UNITRF_1_2[1] )
    DEAD_REGS: {  };
instr: 10
    MC: OP: LOOP LINE:42 UCONDRF_RD:1 BR_OFF:-5,
    B:30 = U1:OUT:0 INSTR_LOG:2|c1#||0 VAR: c1 DATATYPE: INT,
    OUT:2 = B:30 STAGE:-1 VAR: c1 DATATYPE: INT,
    RF:7:IN:0:REG:1 = B:30 STAGE:-1 VAR: c1 DATATYPE: INT,
    //  IN:MC_0: ( ) = LOOP( tmp#7 == UCONDRF_0[1] )
    // OUT:ADDER_1: IADD32 => ( c1 == LATCHRF_2[0], c1 == UNITRF_1_1[1] )
    //  IN:INOUT_2: ( ) = DATA_OUT( c1 == LATCHRF_2[0] )
    DEAD_REGS: {  };
instr: 11
    MC: OP: NONE LINE:-1,
    U0: OP: IADD32 LINE:41 STAGE:-1, // D:\working\im_apps\test\test_kc.i:41
    B:12 = RF:3:OUT:0:REG:1 VAR: sum DATATYPE: INT,
    U0:IN:0 = B:12 VAR: sum DATATYPE: INT,
    B:13 = RF:7:OUT:0:REG:1 VAR: c1 DATATYPE: INT,
    U0:IN:1 = B:13 VAR: c1 DATATYPE: INT,
    //  IN:ADDER_0: ( sum ) = IADD32( sum == UNITRF_0_2[1], c1 == UNITRF_1_1[1] )
    DEAD_REGS: {  };
instr: 12
    MC: OP: NONE LINE:-1,
    B:29 = U0:OUT:0 INSTR_LOG:2|sum#||0 VAR: sum DATATYPE: INT,
    RF:2:IN:0:REG:1 = B:29 STAGE:-1 VAR: sum DATATYPE: INT,
    RF:3:IN:0:REG:1 = B:29 STAGE:-1 VAR: sum DATATYPE: INT,
    // OUT:ADDER_0: IADD32 => ( sum == UNITRF_0_1[1], sum == UNITRF_0_2[1] )
    DEAD_REGS: {  };
instr: 13
    MC: OP: NONE LINE:-1 UCRF_RD:2,
    U7: OP: COMMUCPERM LINE:45 STAGE:-1, // D:\working\im_apps\test\test_kc.i:45
    B:8 = RF:2:OUT:0:REG:1 VAR: sum DATATYPE: INT,
    U7:IN:0 = B:8 VAR: sum DATATYPE: INT,
    B:27 = U7:OUT:0 INSTR_LOG:1|tmp#8#||0 VAR: tmp#8 DATATYPE: INT,
    RF:7:IN:0:REG:1 = B:27 STAGE:-1 VAR: tmp#8 DATATYPE: INT,
    //  IN:COMM_SCHED_0: ( tmp#8 ) = COMMUCPERM( perm_a == UCRF_0[2], sum == UNITRF_0_1[1] )
    // OUT:COMM_SCHED_0: COMMUCPERM => ( tmp#8 == UNITRF_1_1[1] )
    DEAD_REGS: {  };
instr: 14
    MC: OP: NONE LINE:-1,
    U0: OP: IADD32 LINE:45 STAGE:-1, // D:\working\im_apps\test\test_kc.i:45
    B:12 = RF:3:OUT:0:REG:1 VAR: sum DATATYPE: INT,
    U0:IN:0 = B:12 VAR: sum DATATYPE: INT,
    B:13 = RF:7:OUT:0:REG:1 VAR: tmp#8 DATATYPE: INT,
    U0:IN:1 = B:13 VAR: tmp#8 DATATYPE: INT,
    //  IN:ADDER_0: ( sum ) = IADD32( sum == UNITRF_0_2[1], tmp#8 == UNITRF_1_1[1] )
    DEAD_REGS: {  };
instr: 15
    MC: OP: NONE LINE:-1,
    B:29 = U0:OUT:0 INSTR_LOG:2|sum#||0 VAR: sum DATATYPE: INT,
    RF:2:IN:0:REG:1 = B:29 STAGE:-1 VAR: sum DATATYPE: INT,
    RF:9:IN:0:REG:1 = B:29 STAGE:-1 VAR: sum DATATYPE: INT,
    // OUT:ADDER_0: IADD32 => ( sum == UNITRF_0_1[1], sum == UNITRF_1_3[1] )
    DEAD_REGS: {  };
instr: 16
    MC: OP: NONE LINE:-1 UCRF_RD:3,
    U7: OP: COMMUCPERM LINE:47 STAGE:-1, // D:\working\im_apps\test\test_kc.i:47
    B:8 = RF:2:OUT:0:REG:1 VAR: sum DATATYPE: INT,
    U7:IN:0 = B:8 VAR: sum DATATYPE: INT,
    B:27 = U7:OUT:0 INSTR_LOG:1|tmp#9#||0 VAR: tmp#9 DATATYPE: INT,