tda10021.c

LG TDA10021 DVBC linux driver

	tmp =  ((symbolrate << 4) % FIN) << 8;
	ratio = (ratio << 8) + tmp / FIN;
	tmp = (tmp % FIN) << 8;
	ratio = (ratio << 8) + (tmp + FIN/2) / FIN;

	BDR = ratio;
	BDRI = (((XIN << 5) / symbolrate) + 1) / 2;

	if (BDRI > 0xFF)
		BDRI = 0xFF;

	SFIL = (SFIL << 4) | tda10021_inittab[0x0E];

	NDEC = (NDEC << 6) | tda10021_inittab[0x03];
        printk("NDEC=%x,BDR=%x,BDRI=%x,SFIL=%x\n",NDEC,BDR,BDRI,SFIL);
	tda10021_writereg (state, 0x03, NDEC);
	tda10021_writereg (state, 0x0a, BDR&0xff);
	tda10021_writereg (state, 0x0b, (BDR>> 8)&0xff);
	tda10021_writereg (state, 0x0c, (BDR>>16)&0x3f);

	tda10021_writereg (state, 0x0d, BDRI);
	tda10021_writereg (state, 0x0e, SFIL);

	return 0;
}
*/
static int tda10021_init (struct dvb_frontend *fe)
{
	struct tda10021_state* state = fe->demodulator_priv;
	int i;

	dprintk("DVB: TDA10021(%d): init chip\n", fe->adapter->num);

	//tda10021_writereg (fe, 0, 0);

	for (i=0; i<tda10021_inittab_size; i++)
		tda10021_writereg (state, i, tda10021_inittab[i]);

	tda10021_writereg (state, 0x34, state->pwm);

	//Comment by markus
	//0x2A[3-0] == PDIV -> P multiplaying factor (P=PDIV+1)(default 0)
	//0x2A[4] == BYPPLL -> Power down mode (default 1)
	//0x2A[5] == LCK -> PLL Lock Flag
	//0x2A[6] == POLAXIN -> Polarity of the input reference clock (default 0)

	//Activate PLL
	tda10021_writereg(state, 0x2a, tda10021_inittab[0x2a] & 0xef);

	if (state->config->pll_init) {
		lock_tuner(state);
		state->config->pll_init(fe);
		unlock_tuner(state);
	}
	
	
	return 0;
}



static int tda10021_set_parameters (struct dvb_frontend *fe,
			    struct dvb_frontend_parameters *p)
{
	struct tda10021_state* state = fe->demodulator_priv;

	//table for QAM4-QAM256 ready  QAM4  QAM16 QAM32 QAM64 QAM128 QAM256
	//CONF
	static const u8 reg0x00 [] = { 0x14, 0x00, 0x04, 0x08, 0x0c,  0x10 };
	//AGCREF value
	static const u8 reg0x01 [] = { 0x78, 0x8c, 0x8c, 0x6a, 0x78,  0x5c };
	//LTHR value
	static const u8 reg0x05 [] = { 0x78, 0x87, 0x64, 0x46, 0x30/*0x36*/,  0x26 };
	//MSETH
	static const u8 reg0x08 [] = { 0x8c, 0xa2, 0x74, 0x43, 0x30/*0x34*/,  0x23 };
	//AREF
	static const u8 reg0x09 [] = { 0x96, 0x91, 0x96, 0x6a, 0x7e,  0x6b };

	int qam = p->u.qam.modulation;
        //printk("qam=%x\n",qam);
	if (qam < 0 || qam > 5)
		return -EINVAL;

	//printk("tda10021: set frequency to %d qam=%d symrate=%d\n", p->frequency,qam,p->u.qam.symbol_rate);

	lock_tuner(state);
	mdelay(10);
	state->config->pll_set(fe, p);
	unlock_tuner(state);


//ZHU XIAO QING
//LG INIT
//////////////////////////////////////////////////////////////////////////////
	int i;
	u8 pByte[3],bByte,foundgain;
	long lDeltaF;

	pByte[0]  = 0x1c;//AC_sConfig.bPLL_M_Factor;
	pByte[1]  = 0;//AC_sConfig.bPLL_N_Factor;
	pByte[2]  = 0x01;//AC_sConfig.bPLL_P_Factor;
	pByte[2] |= 0x10;//AC_PLL_BYPPLL_BIT;	
	// write the PLL registers with PLL bypassed
	for(i=0;i<3;i++)	
		tda10021_writereg (state, 0x28+i, pByte[i]);

	// enable the PLL
	ChipWriteMasked(state,0x2a, 0x10, 0);
	// enable AGC2 and set PWMREF
	ChipWriteMasked(state,0x2e, 0x08, 0x08);
	//AC_PWMREF_DEF;
	tda10021_writereg(state,0x34,state->pwm/*0x80*/);
	// use internal ADC
	ChipWriteMasked(state,0x1b, 0x01, 0x01);
	ChipWriteMasked(state,0x1b, 0x30, 0x30);
	// use only nyquist gain
	ChipWriteMasked(state,0x03, 0x10, 0);
	// set the acquisition to +/-480ppm
	ChipWriteMasked(state,0x03, 0x08, 0x08);
	// POS_AGC - not in data sheet
	ChipWriteMasked(state,0x02, 0x20, 0x20);
	// set the polarity of the PWM for the AGC
  	ChipWriteMasked(state,0x02, 0x04, 0);
	ChipWriteMasked(state,0x2e, 0x02, 0);
	// set the threshold for the IF AGC
	tda10021_writereg(state,0x3b,m_iIfagcMax);     //m_iIfagcmax
	tda10021_writereg(state,0x3c,m_iIfagcMin);     //m_iIfagcmin
	// set the threshold for the TUN AG
	tda10021_writereg(state,0x35,m_iRfagcMax);     //m_iRfagcmax
	tda10021_writereg(state,0x36,m_iRfagcMin);     //m_iRfagcmin
	// set the counter of saturation to its maximun size
	ChipWriteMasked(state,0x0e, 0x03, 0x03);

	tda10021_writereg(state,0x3d,0x00);

	ChipWriteMasked(state,0x12, 0x01,1);/**/

	ChipWriteMasked(state,0x2b, 0x01, 0x01);
	// set the position of the central coeffcient
	ChipWriteMasked(state,0x06, 0x70, 0x70);
	// set the equalizer type
	ChipWriteMasked(state,0x06, 0x01, 0x1);//was 0
	ChipWriteMasked(state,0x1c, 0x20, 0x20);
	// use the central coef when ENADAPT is set to 0
        ChipWriteMasked(state,0x1c, 0x08, 0x08);
        
	// set ALGOD and deltaF
	//lDeltaF  = (long)uSysClk*5;	lDeltaF /= -8;
	//lDeltaF += 3612500;	lDeltaF *= 2048;lDeltaF /= (long)uSysClk;

	pByte[0] = 0xfc;//(u8)lDeltaF;
	pByte[1] = 0x07;//(u8)(((lDeltaF>>8) & 0x03) | 0x04);
	tda10021_writereg(state,0x37, pByte[0]);
        tda10021_writereg(state,0x38, pByte[1]);
	// set the KAGC to its maximun value
	ChipWriteMasked(state,0x02, 0x03, 0x03);

	// set carrier algorithm parameters and SELCAR
	bByte  = 0x80;	bByte |= (u8)(1 << 2);	bByte |= (u8)(1<< 4);
	tda10021_writereg(state,0x2d,bByte);

	// TS interface 1
	// set to 1 MSB if parallel
	tda10021_writereg(state,0x20, 0x7a);

	//Mpeg interface select!! Parallel or serial
	if(m_iMpegoutput==0)ChipWriteMasked(state,0x20,0x01,0);  //uMpegInterface  0:Parllel  
	else ChipWriteMasked(state,0x20,0x01,1);  //uMpegInterface  1:Serial 

	//Serial interface MSB or LSB first
	if(m_iMpegoutput==1) ChipWriteMasked(state,0x2b, 0x40,(u8)(1<<6)); //uMsbfirst
	else if(m_iMpegoutput==2)ChipWriteMasked(state,0x2b, 0x40,(u8)(0<<6)); //uLsbfirst


//	ChipWriteMasked(state,0x20,0x01,0);/**/

	//MPEg out mode slect!!
	/*int mode;
	mode=m_ctrlMpegmode.GetCurSel();	
	if(mode!=1)m_ctrlMpegmodeBclk.EnableWindow(FALSE);
	else m_ctrlMpegmodeBclk.EnableWindow(TRUE);	
	*/
	if(m_Mpegmode!=1)	ChipWriteMasked(state,0x20, 0x08,(u8)(0<<3));//uMpegoutputmode  0:Mode A  1:Mode B
	else ChipWriteMasked(state,0x20, 0x08,(u8)(1<<3));//uMpegoutputmode  0:Mode A  1:Mode B
	
	// set the MPEG output Mode B clock
	ChipWriteMasked(state,0x20, 0xf0,(u8)(m_MpegmodeBclk)); //uMpegModeBclk

	// set the MPEG output clock polarity
	ChipWriteMasked(state,0x12, 0x01,m_Mpegclk);      //uMpegclockpolarity 1:rising		
	
	// TS interface 2
	ChipWriteMasked(state,0x2b, 0x40, 0);


	// set the BER depth
	ChipWriteMasked(state,0x10, 0xc0,0x80);
	// mpeg out enable insert
	tda10021_writereg(state,0x2c,0x0d);
	// spectrum inv yes;
	ChipWriteMasked(state,0x00, 0x20, (u8)(1<<5));

//////////////////////////////////////////////////////////////////////////////
	tda10021_set_symbolrate (state, p->u.qam.symbol_rate);
/*	tda10021_writereg (state, 0x34, state->pwm);*/
  
        ChipWriteMasked(state,0x00,0x1c,reg0x00[qam]);
	tda10021_writereg (state, 0x01, reg0x01[qam]);
	tda10021_writereg (state, 0x05, reg0x05[qam]);
	tda10021_writereg (state, 0x08, reg0x08[qam]);
	tda10021_writereg (state, 0x09, reg0x09[qam]);
        foundgain=0;
	tda10021_RunAlgo(state,p->u.qam.symbol_rate,&foundgain,1,1);
	

/*
	tda10021_setup_reg0 (state, reg0x00[qam], p->inversion);
*/
	return 0;
}

static int tda10021_read_status(struct dvb_frontend* fe, fe_status_t* status)
{
	struct tda10021_state* state = fe->demodulator_priv;
	int sync;

	*status = 0;
	//0x11[0] == EQALGO -> Equalizer algorithms state
	//0x11[1] == CARLOCK -> Carrier locked
	//0x11[2] == FSYNC -> Frame synchronisation
	//0x11[3] == FEL -> Front End locked
	//0x11[6] == NODVB -> DVB Mode Information
	int i;
	//for(i=0;i<0x3c;i++)
	//	printk("Reg[0x%x]=%x\n",i,tda10021_readreg(state,i));
	sync = tda10021_readreg (state, 0x11);
        //printk("sync=%x\n",sync);
	if (sync & 2)
		*status |= FE_HAS_SIGNAL|FE_HAS_CARRIER;

	if (sync & 4)
		*status |= FE_HAS_SYNC|FE_HAS_VITERBI;

	if (sync & 8)
		*status |= FE_HAS_LOCK;

	return 0;
}

static int tda10021_read_ber(struct dvb_frontend* fe, u32* ber)
{
	struct tda10021_state* state = fe->demodulator_priv;

	u32 _ber = tda10021_readreg(state, 0x14) |
		(tda10021_readreg(state, 0x15) << 8) |
		((tda10021_readreg(state, 0x16) & 0x0f) << 16);
	*ber = 10 * _ber;

	return 0;
}

static int tda10021_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
	struct tda10021_state* state = fe->demodulator_priv;

	u8 gain = tda10021_readreg(state, 0x17);
	*strength = (gain << 8) | gain;

	return 0;
}

static int tda10021_read_snr(struct dvb_frontend* fe, u16* snr)
{
	struct tda10021_state* state = fe->demodulator_priv;

	u8 quality = ~tda10021_readreg(state, 0x18);
	*snr = (quality << 8) | quality;

	return 0;
}

static int tda10021_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
	struct tda10021_state* state = fe->demodulator_priv;

	*ucblocks = tda10021_readreg (state, 0x13) & 0x7f;
	if (*ucblocks == 0x7f)
		*ucblocks = 0xffffffff;

	/* reset uncorrected block counter */
	tda10021_writereg (state, 0x10, tda10021_inittab[0x10] & 0xdf);
	tda10021_writereg (state, 0x10, tda10021_inittab[0x10]);

	return 0;
}

static int tda10021_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
{
	struct tda10021_state* state = fe->demodulator_priv;
	int sync;
	s8 afc = 0;

	sync = tda10021_readreg(state, 0x11);
	afc = tda10021_readreg(state, 0x19);
	if (verbose) {
		/* AFC only valid when carrier has been recovered */
		printk(sync & 2 ? "DVB: TDA10021(%d): AFC (%d) %dHz\n" :
				  "DVB: TDA10021(%d): [AFC (%d) %dHz]\n",
			state->frontend.dvb->num, afc,
		       -((s32)p->u.qam.symbol_rate * afc) >> 10);
	}

	p->inversion = HAS_INVERSION(state->reg0) ? INVERSION_ON : INVERSION_OFF;
	p->u.qam.modulation = ((state->reg0 >> 2) & 7) + QAM_16;

	p->u.qam.fec_inner = FEC_NONE;
	p->frequency = ((p->frequency + 31250) / 62500) * 62500;

	if (sync & 2)
		p->frequency -= ((s32)p->u.qam.symbol_rate * afc) >> 10;

	return 0;
}

static int tda10021_sleep(struct dvb_frontend* fe)
{
	struct tda10021_state* state = fe->demodulator_priv;

	tda10021_writereg (state, 0x1b, 0x02);  /* pdown ADC */
	tda10021_writereg (state, 0x00, 0x80);  /* standby */

	return 0;
}

static void tda10021_release(struct dvb_frontend* fe)
{
	struct tda10021_state* state = fe->demodulator_priv;
	kfree(state);
}

static struct dvb_frontend_ops tda10021_ops;

struct dvb_frontend* tda10021_attach(const struct tda10021_config* config,
				     struct i2c_adapter* i2c,
				     u8 pwm)
{
	struct tda10021_state* state = NULL;
	/* allocate memory for the internal state */
	state = kmalloc(sizeof(struct tda10021_state), GFP_KERNEL);
	if (state == NULL) goto error;

	/* setup the state */
	state->config = config;
	state->i2c = i2c;
	memcpy(&state->ops, &tda10021_ops, sizeof(struct dvb_frontend_ops));
	state->pwm = pwm;
	state->reg0 = tda10021_inittab[0];
	/* check if the demod is there */
	if ((tda10021_readreg(state, 0x1a) & 0xf0) != 0x70) goto error;

	/* create dvb_frontend */
	state->frontend.ops = &state->ops;
	state->frontend.demodulator_priv = state;
	return &state->frontend;

error:
	kfree(state);
	return NULL;
}

static struct dvb_frontend_ops tda10021_ops = {

	.info = {
		.name = "Philips TDA10021 DVB-C",
		.type = FE_QAM,
		.frequency_stepsize = 62500,
		.frequency_min = 51000000,
		.frequency_max = 858000000,
		.symbol_rate_min = (XIN/2)/64,     /* SACLK/64 == (XIN/2)/64 */
		.symbol_rate_max = (XIN/2)/4,      /* SACLK/4 */
	#if 0
		.frequency_tolerance = ???,
		.symbol_rate_tolerance = ???,  /* ppm */  /* == 8% (spec p. 5) */
	#endif
		.caps = 0x400 | //FE_CAN_QAM_4
			FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
			FE_CAN_QAM_128 | FE_CAN_QAM_256 |
			FE_CAN_FEC_AUTO
	},

	.release = tda10021_release,

	.init = tda10021_init,
	.sleep = tda10021_sleep,

	.set_frontend = tda10021_set_parameters,
	.get_frontend = tda10021_get_frontend,

	.read_status = tda10021_read_status,
	.read_ber = tda10021_read_ber,
	.read_signal_strength = tda10021_read_signal_strength,
	.read_snr = tda10021_read_snr,
	.read_ucblocks = tda10021_read_ucblocks,
};

module_param(verbose, int, 0644);
MODULE_PARM_DESC(verbose, "print AFC offset after tuning for debugging the PWM setting");

MODULE_DESCRIPTION("Philips TDA10021 DVB-C demodulator driver");
MODULE_AUTHOR("Ralph Metzler, Holger Waechtler, Markus Schulz");
MODULE_LICENSE("GPL");

EXPORT_SYMBOL(tda10021_attach);