📄 hardware.lst
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.DEFINE C_D2_LatchA 0x0020 //
.DEFINE C_D2_LatchB 0x0040 //
.DEFINE C_D2_LatchAB 0x00C0 //
//... Define for P_LVD_Ctrl ...................
.DEFINE C_LVD24V 0x0000 // LVD = 2.4V
.DEFINE C_LVD28V 0x0001 // LVD = 2.8V
.DEFINE C_LVD32V 0x0002 // LVD = 3.2V
.DEFINE C_LVD36V 0x0003 // LVD = 3.6V
/////////////////////////////////////////////////////////////////
// Note: This register map to the P_INT_Ctrl(0x7010)
// User's interrupt setting have to combine with this register
// while co-work with SACM library.
//
// See. following function for example:
// F_SP_SACM_A2000_Init_:
// F_SP_SACM_S480_Init_:
// F_SP_SACM_S240_Init_:
// F_SP_SACM_MS01_Init_:
// F_SP_SACM_DVR_Init_:
//////////////////////////////////////////////////
00000324 .IRAM
00000324 00 00 .VAR R_InterruptStatus = 0 //
//////////////////////////////////////////////////
.define C_RampDelayTime 16
.define C_QueueSize 100
00000325 00 00 .VAR R_Queue
00000326 00 00 00 00 .DW C_QueueSize-1 DUP(0)
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00
00000389 00 00 .VAR R_ReadIndex
0000038A 00 00 .VAR R_WriteIndex
000096A0 .CODE
///////////////////////////////////////////
// Function: Initial Queue
// Destory: R1,R2
///////////////////////////////////////////
_SP_InitQueue: .PROC
_SP_InitQueue_A2000:
_SP_InitQueue_S480:
_SP_InitQueue_S240:
_SP_InitQueue_MS01:
_SP_InitQueue_DVR:
F_SP_InitQueue_A2000:
F_SP_InitQueue_S480:
F_SP_InitQueue_S240:
F_SP_InitQueue_MS01:
F_SP_InitQueue_DVR:
F_SP_InitQueue:
000096A0 09 93 25 03 R1 = R_Queue
000096A2 40 94 R2 = 0
L_ClearQueueLoop?:
000096A3 D1 D4 [R1++] = R2
000096A4 09 43 89 03 cmp R1, R_Queue+C_QueueSize
000096A6 44 4E jne L_ClearQueueLoop?
000096A7 40 92 R1 = 0
000096A8 19 D3 89 03 [R_ReadIndex] = R1
000096AA 19 D3 8A 03 [R_WriteIndex] = R1
000096AC 90 9A RETF
.ENDP
///////////////////////////////////////////
// Function: Get a data form Queue
// Output: R1: Data
// R2: return value
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue_A2000:
F_SP_ReadQueue_S480:
F_SP_ReadQueue_S240:
F_SP_ReadQueue_MS01:
F_SP_ReadQueue_DVR:
F_SP_ReadQueue:
000096AD 12 95 89 03 R2 = [R_ReadIndex]
000096AF 12 45 8A 03 cmp R2,[R_WriteIndex]
000096B1 0D 5E je L_RQ_QueueEmpty
000096B2 0A 05 25 03 R2 += R_Queue // get queue data address
000096B4 C2 92 R1 = [R2]
000096B5 12 95 89 03 R2 = [R_ReadIndex]
000096B7 41 04 R2 += 1
000096B8 0A 45 64 00 cmp R2, C_QueueSize
000096BA 01 4E jne L_RQ_NotQueueBottom
000096BB 40 94 R2 = 0
L_RQ_NotQueueBottom:
000096BC 1A D5 89 03 [R_ReadIndex] = R2
//r2 = 0x0000 // get queue data
000096BE 90 9A retf
L_RQ_QueueEmpty:
//r2 = 0x8000 // queue empty
000096BF 90 9A retf
///////////////////////////////////////////
// Function: Get a data from Queue but do
// not change queue index
// R1: output
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue_NIC:
F_SP_ReadQueue_NIC_A2000:
F_SP_ReadQueue_NIC_S480:
F_SP_ReadQueue_NIC_S240:
F_SP_ReadQueue_NIC_MS01:
F_SP_ReadQueue_NIC_DVR:
000096C0 12 95 89 03 R2 = [R_ReadIndex]
000096C2 12 45 8A 03 cmp R2,[R_WriteIndex]
000096C4 03 5E je L_RQ_QueueEmpty?
000096C5 0A 05 25 03 R2 += R_Queue // get queue data index
000096C7 C2 92 R1 = [R2]
L_RQ_QueueEmpty?:
000096C8 90 9A RETF
///////////////////////////////////////////
// Function: Put a data to Queue
// R1: Input
// Destory: R1,R2
///////////////////////////////////////////
F_SP_WriteQueue_A2000:
F_SP_WriteQueue_S480:
F_SP_WriteQueue_S240:
F_SP_WriteQueue_MS01:
F_SP_WriteQueue_DVR:
F_SP_WriteQueue:
000096C9 12 95 8A 03 R2 = [R_WriteIndex] // put data to queue
000096CB 0A 05 25 03 R2 += R_Queue
000096CD C2 D2 [R2] = R1
000096CE 12 95 8A 03 R2 = [R_WriteIndex]
000096D0 41 04 R2 += 1
000096D1 0A 45 64 00 cmp R2, C_QueueSize
000096D3 01 4E jne L_WQ_NotQueueBottom
000096D4 40 94 R2 = 0
L_WQ_NotQueueBottom:
000096D5 1A D5 8A 03 [R_WriteIndex] = R2
000096D7 90 9A RETF
///////////////////////////////////////////
// Function: Test Queue Status
// o/p: R1
// Destory: R1
///////////////////////////////////////////
F_SP_TestQueue_A2000:
F_SP_TestQueue_S480:
F_SP_TestQueue_S240:
F_SP_TestQueue_MS01:
F_SP_TestQueue_DVR:
F_SP_TestQueue:
//... Test Queue Empty ...
000096D8 11 93 89 03 R1 = [R_ReadIndex]
000096DA 11 43 8A 03 cmp R1,[R_WriteIndex]
000096DC 12 5E je L_TQ_QueueEmpty
//... Test Queue Full ...
000096DD 11 93 89 03 R1 = [R_ReadIndex] // For N Queue Full: 1.R=0 and W=N-1 2. R<>0 and W=R-1
000096DF 05 4E jnz L_TQ_JudgeCond2
000096E0 11 93 8A 03 R1 = [R_WriteIndex]
000096E2 09 43 63 00 cmp R1, C_QueueSize-1 // Cond1
000096E4 08 5E je L_TQ_QueueFull
L_TQ_JudgeCond2:
000096E5 11 93 89 03 R1 = [R_ReadIndex]
000096E7 41 22 R1 -=1
000096E8 11 43 8A 03 cmp R1,[R_WriteIndex]
000096EA 02 5E je L_TQ_QueueFull
000096EB 40 92 r1 = 0 // not Full, not empty
000096EC 90 9A retf
L_TQ_QueueFull:
000096ED 41 92 r1 = 1 // full
000096EE 90 9A retf
L_TQ_QueueEmpty:
000096EF 42 92 r1 = 2 // empty
000096F0 90 9A retf
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_A2000_Initial()
// or F_SACM_A2000_Initial:
// Note: The following functions are the partial code of original
// initial subroutine. (H/W setting part)
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