📄 add4b.vhd
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-----4 bit adder
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity add4b is
port(cin :in std_logic; --carry in flag;
a,b :in std_logic_vector(3 downto 0);
sum :out std_logic_vector(3 downto 0);
cout:out std_logic--carry out flag;
);
end entity add4b;
architecture behave of add4b is
signal aa,bb :std_logic_vector(4 downto 0);
signal ss :std_logic_vector(4 downto 0);
begin
aa<='0'&a;
bb<='0'&b;
ss<=aa+bb+cin;
sum<=ss(3 downto 0);
cout<=ss(4);
end;
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