📄 ps_change2.vhd
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-----------------------------------------------------------------------
--function :parallet in sereis out, high bit first in,first out;
--并串转换,保证n位数全部串行(左移位,高位在前)输出后,再重新自动置数,再转换
--无人为延时
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ps_change2 is
generic (n : integer :=14 --bits of parallet input
);
port(in_paral :in std_logic_vector(n-1 downto 0);--parallet input
clk :in std_logic;
out_series:out std_logic --series output
);
end entity;
architecture behave of ps_change2 is
signal tmp : std_logic_vector(n-1 downto 0);
signal load: integer range 0 to n; --load=0则置数,否则移位输出
begin
process(clk,tmp)
begin
if(clk'event and clk='1') then
if(load=0) then --load=0,置数
tmp<=in_paral;
load<=n-1; --置需要移位的次数n
out_series<=in_paral(n-1);
else --load不等于0,移位输出
out_series<=tmp(n-2);
tmp(n-1 downto 1)<=tmp(n-2 downto 0);
load<=load-1; --移位一次,load数减一
end if;
end if;
end process;
end behave;
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