delay2clk.vhd

来自「可以很好实现一个二进制转换成BCD码的程序」· VHDL 代码 · 共 29 行

-----clk  delay 2 clk pulse;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity delay2clk is
 port(clk :in std_logic; 
      clk2:out std_logic
     );
end entity delay2clk;

architecture behave of delay2clk is
   signal flag :integer range 0 to 2;
begin
 process(clk)
 begin
  if(flag>=2)  then
   clk2<=clk;
  else 
     if(clk'event and clk='1') then    
      flag<=flag+1;
      clk2<='0';
     end if;
  end if;
 end process;
end behave;