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<!doctype html public "-//W3C//DTD HTML 3.2//EN"><html><head><title>PSR and conditional execution</title><meta http-equiv="content-type" content="text/html; charset=ISO-8859-1" /><meta http-equiv="content-language" content="en" /><meta name="resource-type" content="document"><meta name="copyright" content="This document copyright 2001 by Richard Murray. Use for non-profit and education purposes explicitly granted."><meta name="author" content="Richard Murray"><meta name="rating" content="general"></head><!-- /assembler/psr.html --><!-- --><!-- (C) Copyright 2001 Richard Murray --><!-- Designed by Richard Murray --><!-- rmurray@heyrick.co.uk --><!-- --><body bgcolor="#f0f0f0" text="#000000" link="#0022dd" vlink="#002288"><table border = "0" width="100%"> <tr> <td align=center width=100> <img src="arm3.gif" width=79 height=78 align = middle> </td> <td> <h1 align="center"><font color="#800080">Program Status Register<br>&<br> conditional execution</font></h1> </td> <td align=center width=100> <img src="arm3.gif" width=79 height=78 align = middle> </td></table><p> <p><a href="#32bit">Go here for details of R15/PSR in 32-bit mode.</a><p><h2>Register 15 (26-bit mode):</h2>R15 is built up as follows:<pre> Bit 31 30 29 28 27 26 25------------2 1 0 N Z C V I F Program Counter S1 S0</pre>The flags mean:<pre> N Negative Set if result is negative Z Zero Set if result is zero C Carry Set if carry occurs O Overflow Set if overflow occurs I IRQ Interrupt disable F FIQ Fast Interrupt disable S1 and S0 are processor mode flags: S1 S0 Mode 0 0 USR - User mode 0 1 FIQ - Fast Interrupt mode 1 0 IRQ - Interrupt mode 1 1 SVC - Supervisor mode</pre><p>When R15 is used as the first operand in an instruction, only the Program Counter part of it isavailable. Thus, the following instruction will copy PC out to a register and add 256 to it:<br><code> ADD R0, R15, #256</code><br>(<i>R15</i> and <i>PC</i> mean the same thing to the BASIC assembler)<p>When R15 is used as the second operand, all 32 bits are accessible: the Program Counter, theflags, and the status. The following code segment will identify the current processor mode:<pre> MOV R0, #3 ; Load a bit mask (%11) into R0 AND R0, R0, PC ; AND R15 into R0, to get the mode status CMP R0, #3 ; Compare mode with '3' (SVC) BEQ svc ; If SVC mode, branch to 'svc' CMP R0, #2 ; Compare mode with '2' (IRQ) BEQ irq ; If IRQ mode, branch to 'irq' CMP R0, #1 ; Compare mode with '1' (FIQ) BEQ fiq ; If FIQ mode, branch to 'fiq' CMP R0, #0 ; Compare mode with '0' (USR) BEQ usr ; If USR mode, branch to 'usr'</pre><font color="red">This example is not 32-bit compliant. Refer to <a href="#32bit">the sectionbelow</a> for how to read the current mode in the 32-bit environment.</font><br><div align = right><a href="sw/currmode.basic"><i>Download example: currmode.basic</i></a></div><p><h2>Changing processor status:</h2>In order to change the processor mode, or indeed any of the flags, we need to EOR the desiredflag with the status flags,<br><code> new_state = old_state EOR (1 << 28)</code>could be pseudocode for changing the state of the oVerflow flag. But we cannot do a simple<code>EORS</code> operation as the pipeline would cause the following two instructions to beskipped.<br>But don't worry. The instruction <code>TEQ</code> does a pretend EOR (the results are notstored anywhere). Combine this with the <code>P</code> suffix, which writes bits 0, 1, and 26 to31 of the result directly to bits 0, 1, and 26 to 31 of R15 giving you an easy way to changethe flags:<code> TEQP R15, bit_mask</code><p<i>You can only change a flag if you are in a processor mode which allows you to set thatflag.</i><br><font color="red">This example is not 32-bit compliant. Refer to <a href="#32bit">the sectionbelow</a> for how to change modes in the 32-bit environment.</font><p>This can be expanded to change processor mode. For example, to enter SVC mode you would:<pre> MOV R6, PC ; Store original state of PC in R6 ORR R7, R6, #3 ; Set SVC mode TEQP R7, #0 ; Write mode flags (in R7) to PC</pre>And to return to the original mode:<pre> TEQP R6, #0 ; Write previous mode flags (in R6) to PC</pre><div align = right><a href="sw/setmode.basic"><i>Download example: setmode.basic</i></a></div><p>After changing the mode, you should perform a null operation to allow the registers to settle.Something like <code>MOV R0, R0</code> should be okay. The use of <i>NV</i> suffixedinstructions has been deprecated.<p> <p> <p><h2>Conditional execution:</h2>A <i>very</i> special feature of the ARM processor is its conditional execution. We are nottalking your basic <code>Branch if Carry Set</code>, the ARM takes this a logical stage furtherto mean <code>XXX if carry set</code> - where XXX is just about anything.<p>By way of example, here is a list of branch instructions understood by the Intel 8086 processor:<pre> JA Jump if Above JAE Jump if Above or Equal JB Jump if Below JBE Jump if Below or Equal JC Jump if Carry JCXZ Jump if CX Zero (CX is a register that can be used for loop counts) JE Jump if Equal JG Jump if Greater than JGE Jump if Greater than or Equal JL Jump if Less than JLE Jump if Less Than or Equal JMP JuMP JNA Jump if Not Above JNAE Jump if Not Above or Equal JNB Jump if Not Below JNBE Jump if Not Below or Equal JNC Jump if No Carry JNE Jump if Not Equal JNG Jump if Not Greater than JNGE Jump if Not Greater than or Equal JNL Jump if Not Less than JNLE Jump if Not Less than or Equal JNO Jump if Not Overflow JNP Jump if Not Parity JNS Jump if Not Sign JNZ Jump if Not Zero JO Jump if Overflow JP Jump if Parity JPE Jump if Parity Even JPO Jump if Parity Odd JS Jump if Sign JZ Jump if ZeroAnd the 80386 added: JECXZ Jump if ECX Zero</pre>And by contrast, the ARM processor offers a whopping...uh...<pre> B Branch BL Branch with Link</pre>But the ARM is not limited by this seemingly inflexible approach due to conditional executionwhich offers you:<pre> BEQ Branch if EQual BNE Branch if Not Equal BVS Branch if oVerflow Set BVC Branch if oVerflow Clear BHI Branch if HIgher BLS Branch if Lower or the Same BPL Branch if PLus BMI Branch if MInus BCS Branch if Carry Set BCC Branch if Carry Clear BGE Branch if Greater than or Equal BGT Branch if Greater Than BLE Branch if Less than or Equal BLT Branch if Less Than BLEQ Branch with Link if EQual .... BLLT Branch with Link if Less Than</pre>There are two more codes,<ul> <li> <code>AL</code> - ALways, the default condition so doesn't need to be specified <li> <code>NV</code> - NeVer, so very useful. You should not use this code anyway...</ul>The crunch comes, however, when you realise that all of the Bxx instructions are actually<i>the same instruction</i>. Then you will think, if you can do all that to a branch instruction,can it be done to, say, a register load instruction?<br>The answer is yes.<p> <p> <p>Here follows a list of available conditional codes:<dl> <dt> EQ : Equal <dd> If the Z flag is set after a comparison.</dl><p><dl> <dt> NE : Not Equal <dd> If the Z flag is clear after a comparison.</dl><p><dl> <dt> VS : Overflow Set <dd> If the V flag is set after an arithmetical operation, the result of which will not fit into a 32bit destination register.</dl><p><dl> <dt> VC : Overflow Clear <dd> If the V flag is clear, the reverse of VS.</dl><p><dl> <dt> HI : Higher Than (unsigned) <dd> If after a comparison the C flag is set <b>AND</b> the Z flag is clear.</dl><p><dl> <dt> LS : Lower Than or Same (unsigned) <dd> If after a comparison the C flag is clear <b>OR</b> the Z flag is set.</dl><p><dl> <dt> PL : Plus <dd> If the N flag is clear after an arithmetical operation. For the purposes of defining 'plus', zero is positive because it isn't negative...</dl><p><dl> <dt> MI : Minus <dd> If the N flag is set after an arithmetical operation.</dl><p><dl> <dt> CS : Carry Set <dd> Set if the C flag is set after an arithmetical operation OR a shift operation, the result of which cannot be represented in 32bits. You can think of the C flag as the 33rd bit of the result.</dl><p><dl> <dt> CC : Carry Clear <dd> The reverse of CS.</dl><p><dl> <dt> GE : Greater Than or Equal (signed) <dd> If after a comparison...<br> the N flag is set <b>AND</b> the V flag is set<br> or...<br> the N flag is clear <b>AND</b> the V flag is clear.</dl><p><dl> <dt> GT : Greater Than (signed) <dd> If after a comparison...<br> the N flag is set <b>AND</b> the V flag is set<br> or...<br> the N flag is clear <b>AND</b> the V flag is clear<br> <i><b>and</b></i>...<br> the Z flag is clear.</dl><p><dl> <dt> LE : Less Than or Equal To (signed) <dd> If after a comparison...<br> the N flag is set <b>AND</b> the V flag is clear<br> or...<br> the N flag is clear <b>AND</b> the V flag is set<br> <i><b>and</b></i>...<br> the Z flag is set.</dl><p><dl> <dt> LT : Less Than (signed) <dd> If after a comparison...<br> the N flag is set <b>AND</b> the V flag is clear<br> or...<br> the N flag is clear <b>AND</b> the V flag is set.⌨️ 快捷键说明
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