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<!doctype html public "-//W3C//DTD HTML 3.2//EN"><html><head><title>Processor setup via co-processor 15</title><meta http-equiv="content-type" content="text/html; charset=ISO-8859-1" /><meta http-equiv="content-language" content="en" /><meta name="resource-type" content="document"><meta name="copyright" content="This document copyright 2001 by Richard Murray. Use for non-profit and education purposes explicitly granted."><meta name="author" content="Richard Murray"><meta name="rating" content="general"></head><!-- /assembler/coprocmnd.html --><!-- --><!-- (C) Copyright 2001 Richard Murray --><!-- Designed by Richard Murray --><!-- rmurray@heyrick.co.uk --><!-- --><body bgcolor="#f0f0f0" text="#000000" link="#0022dd" vlink="#002288"><table border = "0" width="100%"> <tr> <td align=center width=100> <img src="arm3.gif" width=79 height=78 align = middle> </td> <td> <h1 align="center"><font color="#800080">Processor setup via co-processor 15</font></h1> </td> <td align=center width=100> <img src="arm3.gif" width=79 height=78 align = middle> </td></table><p> <p><h2>Introduction</h2>ARM processors after (and including) the ARM 3 offer various ID and internal configurationfacilities by providing internally a co-processor 15 which you can read from and and write to.<p>The setup is controlled by co-processor 15 registers, accessed with <i>MRC</i> and <i>MCR</i> innon-user mode.<p>These registers are particular to the processor specified.<p> <p> <p><h2>ARM 3</h2><ul> <li> Register 0 - <b>Processor identification</b> (read only)<br><pre> Bits 0 - 7 Revision of processor Bits 8 - 15 Should be '3', identifying processor as an ARM3 Bits 16 - 23 Manufacturer code (&56 = VLSI Technology Inc.) Bits 24 - 31 Designer code (&41 = ARM Ltd)</pre> <br> <br> <li> Register 1 - <b>Cache flush</b> (write only)<br> Write-sensitive, writing anything to register 1 will cause the cache to be flushed. <br> <br> <li> Register 2 - <b>Miscellaneous control</b><br><pre> Bit 0 - Turns the cache on (1) or off (0) Bit 1 - Determines if user mode and non-user mode use the same address mapping. 1 if they do, or 0. Should be 1 for use with MEMC. Bit 2 - 0 for normal operation, 1 for special monitor mode (processor runs at memory speed and address/data always put on external pins even if data fetched from cache - for logic analyser to trace the program properly). Other bits reserved.</pre> <br> <br> <li> Register 3 - <b>Which areas are cacheable</b><br> Controls which areas of memory are cacheable, in 2Mb chunks.<pre> Bit 0 - 1 if virtual addresses &0000000-&01FFFFF are cacheable, 0 if not Bit 0 - 1 if virtual addresses &0200000-&03FFFFF are cacheable, 0 if not ... Bit 31 - 1 if virtual addresses &3E00000-&3FFFFFF are cacheable, 0 if not</pre> <br> <br> <li> Register 4 - <b>Which areas are updateable</b><br> Controls which areas of memory are updateable, in 2Mb chunks. Writes to non-updateable memory go to the real memory, not the cache. This is suitable for things like ROMs, since you don't want the cached data to be altered by attempted writes.<pre> Bit 0 - 1 if virtual addresses &0000000-&01FFFFF are updateable, 0 if not Bit 0 - 1 if virtual addresses &0200000-&03FFFFF are updateable, 0 if not ... Bit 31 - 1 if virtual addresses &3E00000-&3FFFFFF are updateable, 0 if not</pre> <br> <br> <li> Register 5 - <b>Which areas are distruptive</b><br> Controls which areas of memory are distruptive, in 2Mb chunks. Writes to distruptive areas of memory cause the cache to be flushed. For example, writing to physical memory at &2000000-&2FFFFFF on an MEMC system will usually cache virtually addresses memory and if this location was cached, an attempt to read it would read back the old contents.<pre> Bit 0 - 1 if virtual addresses &0000000-&01FFFFF are distruptive, 0 if not Bit 0 - 1 if virtual addresses &0200000-&03FFFFF are distruptive, 0 if not ... Bit 31 - 1 if virtual addresses &3E00000-&3FFFFFF are distruptive, 0 if not</pre></ul>Register 2 is set to zero after power-up, and registers 3-5 are undefined. The registers 3-5should be set up correctly before the cache is switched on. You should always check the processoridentity before setting up the registers, unless you are completely certain your code will onlyever be executed on an ARM3 processor.<p> <p> <p><h2>ARM 610</h2><ul> <li> Register 0 - <b>Processor identification</b> (read only)<br> The value returned for an ARM610 processor should be &4156061x.<br><pre> Bits 0 - 7 Revision of processor (&1x) Bits 8 - 15 Processor identity Bits 16 - 23 Manufacturer code (&56 = VLSI Technology Inc.) Bits 24 - 31 Designer code (&41 = ARM Ltd)</pre> <br> <br> <li> Register 1 - <b>Control</b> (write only)<br> All values set to 0 at power-up.<br><pre> Bit 0 - On-chip MMU turned off (0) or on (1) Bit 1 - Address alignment fault disabled (0) or enabled (1) Bit 2 - Instruction/data cache turned off (0) or on (1) Bit 3 - Write buffer turned off (0) or on (1) Bit 4 - 26 bit program space if 0, 32 bit program space if 1 Bit 5 - 26 bit data space if 0, 32 bit data space if 1 Bit 6 - Early abort mode if 0, late abort mode if 1 Bit 7 - Little-endian operation if 0, big-endian if 1 Bit 8 - System bit - controls the ARM610 permission system</pre> <br> <br> <li> Register 2 - <b>Translation Table Base</b> (write only)<br> Bits 14-31 hold the base of the currently active Level One page table. <br> <br> <li> Register 3 - <b>Domain Access Control</b> (write only)<br> This register holds the current access control for domains 0 to 15. Each domain has two bits (domain 0 bits 0,1 ... domain 15 bits 30,31) which may be set as follows:<pre> 00 No Access - Domain fault generated if tried to access 01 Client - Accesses are checked against permission bits in section/page descriptor 10 Reserved - Currently behaves like no access mode 11 Manager - Accesses are NOT checked, permission faults cannot be generated</pre> <br> <br> <li> Register 4 - <b>Reserved</b> - do not attempt to access <br> <br> <li> Register 5 - <b>Page fault status / TLB flush</b><br> When reading, this holds the status of the last data fault (not updated for prefetch fault). Only the bottom byte is of significance.<pre> Bits 0 - 3 Status Bits 4 - 7 Domain Bits 8 - 11 Set to zero Bits 12 - 31 Whatever was the last value on the internal data bus</pre><br> <br> When writing to this register, any value written will cause the Translation Look-aside Buffer to be flushed. <br> <br> <li> Register 6 - <b>Data fault address / TLB purge</b><br> When reading this register, you can determine the virtual address of the last page fault. <br> <br> When writing this register, the value given (in bits 14-31) is treated as an address. The TLB will be searched for a corresponding address and if it is found, it is marked as invalid. This is to allow the page table in main memory to be updated and the now-invalid entries in the on-chip TLB to be purged without assuming the penalty of flushing the entire TLB. <br> <br> <li> Register 7 - <b>IDC flush</b> (write only)<br> Any data written to this location will cause the IDC (Instruction/Data cache) to be flushed. <br> <br> <li> Registers 8 to 15 - <b>Reserved</b><br> Accessing these registers will cause the undefined instruction trap to be taken.</ul><p> <p> <p><h2>ARM 710</h2>This is similar to the ARM610.<ul> <li> Register 0 - <b>Processor identification</b> (read only)<br> The value returned for an ARM610 processor should be &4104710x.<br><pre> Bits 0 - 3 Revision of processor? Bits 3 - 15 Processor identity - &710 Bits 16 - 23 Manufacturer code Bits 24 - 31 Designer code (&41 = ARM Ltd)</pre> <br> <br> <li> Register 1 - <b>Control</b> (write only)<br> All values set to 0 at power-up.<br><pre> Bit 0 - On-chip MMU turned off (0) or on (1) Bit 1 - Address alignment fault disabled (0) or enabled (1) Bit 2 - Instruction/data cache turned off (0) or on (1) Bit 3 - Write buffer turned off (0) or on (1) Bit 4 - 26 bit program space if 0, 32 bit program space if 1 Bit 5 - 26 bit data space if 0, 32 bit data space if 1 Bit 6 - Early abort mode if 0, late abort mode if 1 Bit 7 - Little-endian operation if 0, big-endian if 1 Bit 8 - System bit - controls the ARM710 permission system Bit 9 - ROM bit - controls the ARM710 permission system</pre> <br> <br> <li> Register 2 - <b>Translation Table Base</b> (write only)<br> Bits 14-31 hold the base of the currently active Level One page table. <br> <br> <li> Register 3 - <b>Domain Access Control</b> (write only)<br> This register holds the current access control for domains 0 to 15. Each domain has two bits (domain 0 bits 0,1 ... domain 15 bits 30,31) which may be set as follows:<pre> 00 No Access - Domain fault generated if tried to access 01 Client - Accesses are checked against permission bits in section/page descriptor 10 Reserved - Currently behaves like no access mode 11 Manager - Accesses are NOT checked, permission faults cannot be generated</pre> <br> <br> <li> Register 4 - <b>Reserved</b> - do not attempt to access <br> <br> <li> Register 5 - <b>Page fault status / TLB flush</b><br> When reading, this holds the status of the last data fault (not updated for prefetch fault). Only the bottom byte is of significance.<pre> Bits 0 - 3 Status Bits 4 - 7 Domain Bits 8 - 11 Set to zero Bits 12 - 31 Whatever was the last value on the internal data bus</pre><br> <br> When writing to this register, any value written will cause the Translation Look-aside Buffer to be flushed. <br> <br> <li> Register 6 - <b>Data fault address / TLB purge</b><br> When reading this register, you can determine the virtual address of the last page fault. <br> <br> When writing this register, the value given (in bits 14-31) is treated as an address. The TLB will be searched for a corresponding address and if it is found, it is marked as invalid. This is to allow the page table in main memory to be updated and the now-invalid entries in the on-chip TLB to be purged without assuming the penalty of flushing the entire TLB. <br> <br> <li> Register 7 - <b>IDC flush</b> (write only)<br> Any data written to this location will cause the IDC (Instruction/Data cache) to be flushed. <br> <br> <li> Registers 8 to 15 - <b>Reserved</b><br> Accessing these registers will cause the undefined instruction trap to be taken.</ul><p> <p> <p><h2>ARM 7500</h2>The registers are exactly the same as the ARM710, except the processor ID (register 0) will bedifferent. The datasheet did not specify what should be expected.<p> <p> <p><h2>ARM 7500FE</h2>The registers are exactly the same as the ARM710, except the processor ID (register 0) will bedifferent. The datasheet did not specify what should be expected.<p> <p><hr size = 3><a href="index.html#03">Return to assembler index</a><hr size = 3><address>Copyright © 2001 Richard Murray</address></body></html>⌨️ 快捷键说明
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