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关于ARM汇编的非常好的教程

      This was also true of the early CISC processors, but these days a typical CISC processor
      has a heart which executes microcode instructions which co-relate to the instructions
      passed into the processor. Ironically, this 'heart' tends to be RISC. <tt>:-)</tt>
      <br>&nbsp;<br>

  <li>As touched on my Matthias below, a RISC processor's simplicity does not necessarily refer
      to a simple instruction set.<br>
      He quotes <code>LDREQ R0,[R1,R2,LSR #16]!</code>, though I would prefer to quote the 26
      bit instruction <code>LDMEQFD R13!, {R0,R2-R4,PC}^</code> which restores R0, R2, R3, R4,
      and R15 from the fully descending stack pointed to by R13. The stack is adjusted
      accordingly. The '^' pushes the processor flags into R15 as well as the return address. And
      it is conditionally executed. This allows a tidy 'exit from routine' to be performed in a
      single instruction.<br>
      Powerful, isn't it?<br>
      The RISC concept, however, does not state that all the instructions are simple. If that
      were true, the ARM would not have a MUL, as you can do the exact same thing with looping
      ADDing. No, the RISC concept means the silicon is simple. It is a simple processor to
      implement.<br>
      I'll leave it as an exercise for the reader to figure out the power of Mathias' example
      instruction. It is exactly on par with my example, if not slightly more so!
</ul>

For a completion of this summary, and some very good points regarding the ARM processor, keep
reading...
<p>&nbsp;<p>


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<a name="reply"></a>
<p>

In response to the original version of this text,
<a href="http://www.deutschlandwetter.de/">Matthias Seifert</a> <font color = "red" size = "-1">[EXTERNAL LINK]</font> replied with a more specific and
detailed analysis. He has kindly allowed me to reproduce his message here...
<p>&nbsp;<p>

<h2 align=center>RISC vs ARM</h2>

You shouldn't call it &quot;RISC vs CISC&quot; but &quot;ARM vs CISC&quot;. For example
conditional execution of (almost) any instruction isn't a typical feature of RISC processors but
can only(?) be found on ARMs. Furthermore there are quite some people claiming that an ARM isn't
really a RISC processor as it doesn't provide only a simple instruction set, i.e. you'll hardly
find any CISC processor which provides a single instruction as powerful as a
<pre>  LDREQ R0,[R1,R2,LSR #16]!
</pre>

Today it is wrong to claim that CISC processors execute the complex instructions more slowly,
modern processors can execute most complex instructions with one cycle. They may need very long
pipelines to do so (up to 25 stages or so with a Pentium III), but nonetheless they can. And
complex instructions provide a big potential of optimisation, i.e. if you have an instruction
which took 10 cycles with the old model and get the new model to execute it in 5 cycles you end
up with a speed increase of 100% (without a higher clock frequency). On the other hand ARM
processors executed most instruction in a sincle cycle right from the start and thus don't have
this optimisation potential (except the MUL instruction).
<p>

The argument that RISC processors provide more registers than CISC processors isn't right. Just
take a look at the (good old) 68000, it has about the same number of registers as the ARM has.
And that 80x86 compatible processors don't provide more registers is just a matter of
compatibility (I guess). But this argument isn't completely wrong: RISC processors are much
simpler than CISC processors and thus take up much less space, thus leaving space for additional
functionality like more registers. On the other hand, a RISC processor with only three or so
registers would be a pain to program, i.e. RISC processors simply need more registers than CISC
processors for the same job.
<p>

And the argument that RISC processors have pipelining whereas CISCs don't is plainly wrong. I.e.
the ARM2 hadn't whereas the Pentium has...
<p>

The advantages of RISC against CISC are those today:

<ul>
  <li> RISC processors are much simpler to build, by this again results in the following
       advantages:
       <ul>
         <li> easier to build, i.e. you can use already existing production facilities
         <li> much less expensive, just compare the price of a XScale with that of a Pentium III
              at 1 GHz...
         <li> less power consumption, which again gives two advantages:
              <ul>
                <li> much longer use of battery driven devices
                <li> no need for cooling of the device, which again gives to advantages:
                     <ul>
                       <li> smaller design of the whole device
                       <li> no noise
                     </ul>
              </ul>
       </ul>
       <br>&nbsp;<br>

  <li> RISC processors are much simpler to program which doesn't only help the assembler
       programmer, but the compiler designer, too. You'll hardly find any compiler which uses
       all the functions of a Pentium III optimally...
</ul>
<p>

And then there are the benefits of the ARM processors:

<ul>
  <li> Conditional execution of most instructions, which is a very powerful thing especially
       with large pipelines as you have to fill the whole pipeline every time a branch is taken,
       that's why CISC processors make a huge effort for branch prediction
       <br>&nbsp;<br>

  <li> The shifting of registers while other instructions are executed which mean that shifts
       take up no time at all (the 68000 took one cycle per bit to shift)
       <br>&nbsp;<br>

  <li> The conditional setting of flags, i.e. ADD and ADDS, which becomes extremely powerful
       together with the conditional execution of instructions
       <br>&nbsp;<br>

  <li> The free use of offsets when accessing memory, i.e.
<pre>    LDR R0,[R1,#16]
    LDR R0,[R1,#16]!
    LDR R0,[R1],#16
    LDR R0,[R1,R2]
    LDR R0,[R1,R2]!
    LDR R0,[R1],R2
    ...</pre>
       The 68000 could only increase the address register by the size of the data read (i.e. by
       1, 2 or 4). Just imagine how much better an ARM processor can be programmed to draw (not
       only) a vertical line on the screen.
       <br>&nbsp;<br>

  <li> The (almost) free use of all registers with all instructions (which may well be an
       advantage of any RISC processor). It simply is great to be able to use
<pre>    ADD PC,PC,R0,LSL #2
    MOV R0,R0
    B R0is0
    B R0is1
    B R0is2
    B R0is3
    ...</pre>
       or even
<pre>    ADD PC,PC,R0,LSL #3
    MOV R0,R0
    MOV R1,#1
    B Continue
    MOV R2,#2
    B Comtinue
    MOV R2,#4
    B Continue
    MOV R2,#8
    B Continue
    ...</pre>
       I used this technique when programming my C64 emulator even more excessively to emulate
       the 6510. There the shift is 8 which gives 256 bytes for each instruction to emulate.
       Within those 256 bytes there is not only the code for the emulation of the instruction
       but also the code to react on interrupts, the fetching of the next instruction and the
       jump to the emulation code of that instruction, i.e. the code to emulate the CLC (clear C
       flag) looks like this:
<pre>    ADD     R10,R10,#1            ; increment PC of 6510 to point to next
                                  ; instruction
    BIC     R6,R6,#1              ; clear C flag of 6510 status register
    LDR     R0,[R12,#64]          ; read 6510 interrupt state
    CMP     R0,#0                 ; interrupt occured?
    BNE     &00018040             ; yes -> jump to interrupt handler
    LDRB    R1,[R4,#1]!           ; read next instruction
    ADD     PC,R5,R1,LSL #8       ; jump to emulation code
    MOV     R0,R0                 ; lots of these to fill up the 256 bytes</pre>
       This means that there is only one single jump for each instruction emulated. By this (and
       a bit more) the emulator is able to reach 76% of the speed of the original C64 with an
       A3000, 116% with an A4000, 300% with an A5000 and 3441% with my RiscPC (SA at 287 MHz).
       The code may look hard to handle, but the source of it looks much better:
<pre>     ;-----------;
     ; $18 - CLC ;
     ;-----------;
     ADD R10,R10,#1               ; increment PC of 6510
     BIC R6,R6,#%00000001         ; clear C flag of 6510 status register
     FNNextCommand                ; do next command
     FNFillFree                   ; fill remaining space</pre>
</ul>
<p>&nbsp;<p>


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<p>

<h2 align=center>My reply to his reply (!)</h2>

The RISC/CISC debate continues. Looking in a few books, it would seem to come down to whether or
not microcode is used - thus <i>R</i>ISC or <i>C</i>ISC is determined more by the actual physical
design of the processor than by what instructions or how many registers it offers. This would
support the view that some maintain that the 6502 was an early RISC processor. But I'm not going
there...
<p>

My other comment... 3441%. Wow.
<p>&nbsp;<p>


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<address>Copyright &copy; 2002 Richard Murray</address>
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