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<!doctype html public "-//W3C//DTD HTML 3.2//EN"><html><head><title>RISC vs CISC</title><meta http-equiv="content-type" content="text/html; charset=ISO-8859-1" /><meta http-equiv="content-language" content="en" /><meta name="resource-type" content="document"><meta name="copyright" content="This document copyright 2002 by Richard Murray. Use for non-profit and education purposes explicitly granted."><meta name="author" content="Richard Murray"><meta name="rating" content="general"></head><!-- /assembler/riscvcisc.html --><!-- --><!-- (C) Copyright 2002 Richard Murray --><!-- Designed by Richard Murray --><!-- rmurray@heyrick.co.uk --><!-- --><body bgcolor="#f0f0f0" text="#000000" link="#0022dd" vlink="#002288"><table border = "0" width="100%"> <tr> <td align=center width=100> <img src="arm3.gif" width=79 height=78 align = middle> </td> <td> <h1 align="center"><font color="#800080">RISC<br>vs<br>CISC</font></h1> </td> <td align=center width=100> <img src="arm3.gif" width=79 height=78 align = middle> </td></table><p> <p>You can read a reply to this text <a href="#reply">by going here</a>.<p> <p>In the early days of computing, you had a lump of silicon which performed a number ofinstructions. As time progressed, more and more facilities were required, so more and moreinstructions were added. However, according to the 20-80 rule, 20% of the available instructionsare likely to be used 80% of the time, with some instructions only used very rarely. Some ofthese instructions are very complex, so creating them in silicon is a very arduous task. Instead,the processor designer uses microcode. To illustrate this, we shall consider a modern CISCprocessor (such as a Pentium or 68000 series processor). The core, the base level, is a fastRISC processor. On top of that is an interpreter which 'sees' the CISC instructions, and breaksthem down into simpler RISC instructions.<p>Already, we can see a pretty clear picture emerging. Why, if the processor is a simple RISC unit,don't we use that? Well, the answer lies more in politics than design. However Acorn saw this andnot being constrained by the need to remain totally compatible with earlier technologies, theydecided to implement their own RISC processor.<p>Up until now, we've not really considered the real differences between RISC and CISC, so...<p>A <i>Complex Instruction Set Computer</i> (CISC) provides a large and powerful range ofinstructions, which is less flexible to implement. For example, the 8086 microprocessor familyhas these instructions:<pre> JA Jump if Above JAE Jump if Above or Equal JB Jump if Below ... JPO Jump if Parity Odd JS Jump if Sign JZ Jump if Zero</pre>There are 32 jump instructions in the 8086, and the 80386 adds more. I've not read a spec sheetfor the Pentium-class processors, but I suspect it (and MMX) would give me a heart attack!<p>By contrast, the <i>Reduced Instruction Set Computer</i> (RISC) concept is to identify thesubcomponents and use those. As these are much simpler, they can be implemented directly insilicon, so will run at the maximum possible speed. Nothing is 'translated'. There are only twoJump instructions in the ARM processor - Branch and Branch with Link. The "if equal, ifcarry set, if zero" type of selection is handled by condition options, so for example:<pre> BLNV Branch with Link NeVer (useful!) BLEQ Branch with Link if EQual</pre>and so on. The <code>BL</code> part is the instruction, and the following part is the condition.This is made more powerful by the fact that conditional execution can be applied to <i>most</i>instructions! This has the benefit that you can test something, then only do the next fewcommands if the criteria of the test matched. No branching off, you simply add conditional flagsto the instructions you require to be conditional:<pre> SWI "OS_DoSomethingOrOther" ; call the SWI MVNVS R0, #0 ; If failed, set R0 to -1 MOVVC R0, #0 ; Else set R0 to 0</pre>Or, for the 80486:<pre> INT $...whatever... ; call the interrupt CMP AX, 0 ; did it return zero? JE failed ; if so, it failed, jump to fail code MOV DX, 0 ; else set DX to 0 return RET ; and return failed MOV DX, 0FFFFH ; failed - set DX to -1 JMP return</pre>The odd flow in that example is designed to allow the fastest non-branching throughput in the'did not fail' case. This is at the expense of two branches in the 'failed' case.<br>I am not, however, an x86 coder, so that can possibly be optimised - mail me if you have anysuggestions...<p> <p>Most modern CISC processors, such as the Pentium, uses a fast RISC core with an interpretersitting between the core and the instruction. So when you are running Windows95 on a PC, it isnot that much different to trying to get W95 running on the software PC emulator. Just imaginethe power hidden inside the Pentium...<p>Another benefit of RISC is that it contains a large number of registers, most of which can beused as general purpose registers.<p>This is not to say that CISC processors cannot have a large number of registers, some do. Howeverfor it's use, a typical RISC processor requires more registers to goive it additionalflexibility. Gone are the days when you had two general purpose registers and an 'accumulator'.<p>One thing RISC does offer, though, is register independence. As you have seen above the ARMregister set defines at minimum R15 as the program counter, and R14 as the link register(although, after saving the contents of R14 you can use this register as you wish). R0 to R13can be used in any way you choose, although the Operating System defines R13 is used as a stackpointer. You can, if you don't require a stack, use R13 for your own purposes. APCS appliesfirmer rules and assigns more functions to registers (such as Stack Limit). However, none ofthese - with the exception of R15 and sometimes R14 - is a constraint applied by the processor.You do not need to worry about saving your accumulator in long instructions, you simply make gooduse of the available registers.<p>The 8086 offers you fourteen registers, but with caveats:<br>The first four (A, B, C, and D) are Data registers (a.k.a. scratch-pad registers). They are 16bitand accessed as two 8bit registers, thus register A is really AH (A, high-order byte) and AL (Alow-order byte). These can be used as general purpose registers, but they can also have dedicatedfunctions - Accumulator, Base, Count, and Data.<br>The next four registers are Segment registers for Code, Data, Extra, and Stack.<br>Then come the five Offset registers: Instruction Pointer (PC), SP and BP for the stack, then SIand DI for indexing data.<br>Finally, the flags register holds the processor state.<br>As you can see, most of the registers are tied up with the bizarre memory addressing scheme usedby the 8086. So only four general purpose registers are available, and even they are not asflexible as ARM registers.<p>The ARM processor differs again in that it has a reduced number of instruction classes (DataProcessing, Branching, Multiplying, Data Transfer, Software Interrupts).<p>A final example of minimal registers is the 6502 processor, which offers you:<br><code> Accumulator - for results of arithmetic instructions<br> X register - First general purpose register<br> Y register - Second general purpose register<br> PC - Program Counter<br> SP - Stack Pointer, offset into page one (at &01xx).<br> PSR - Processor Status Register - the flags.</code><br>While it might seem like utter madness to only have <i>two</i> general purpose registers,the 6502 was a very popular processor in the '80s. Many famous computers have been builtaround it.<br>For the Europeans: consider the Acorn BBC Micro, Master, Electron...<br>For the Americans: consider the Apple2 and the Commadore PET.<br>The ORIC uses a 6502, and the C64 uses a variant of the 6502.<br>(in case you were wondering, the Speccy uses the <i>other</i> popular processor - the everbizarre and freaky Z80)<p>So if entire systems could be created with a 6502, imagine the flexibility of the ARMprocessor.<br>It has been said that the 6502 is the bridge between CISC design and RISC. Acorn chose the6502 for their original machines such as the Atom and the System# units. They went fromthere to design their own processor - the ARM.<p> <p>To summarise the above, the advantages of a RISC processor are:<ul> <li>Quicker time-to-market. A smaller processor will have fewer instructions, and the design will be less complicated, so it may be produced more rapidly. <br> <br> <li>Smaller 'die size' - the RISC processor requires fewer transistors than comparable CISC processors...<br> This in turn leads to a smaller silicon size (I once asked Russell King of ARMLinux fame where the StrongARM processor was - and I was looking right at it, it is that small!)<br> ...which, in turn again, leads to less heat dissipation. Most of the heat of my ARM710 is actually generated by the 80486 in the slot beside it (and that's when it is supposed to be in 'standby'). <br> <br> <li>Related to all of the above, it is a much lower power chip. ARM design processors in static form so that the processor clock can be stopped completely, rather than simply slowed down. The Solo computer (designed for use in third world countries) is a system that will run from a 12V battery, charging from a solar panel. <br> <br> <li>Internally, a RISC processor has a number of hardwired instructions.<br>⌨️ 快捷键说明
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