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📁 关于ARM汇编的非常好的教程
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<!doctype html public "-//W3C//DTD HTML 3.2//EN"><html><head><title>Processor differences</title><meta http-equiv="content-type" content="text/html; charset=ISO-8859-1" /><meta http-equiv="content-language" content="en" /><meta name="resource-type" content="document"><meta name="copyright" content="This document copyright 2001 by Richard Murray. Use for non-profit and education purposes explicitly granted."><meta name="author" content="Richard Murray"><meta name="rating" content="general"></head><!--  /assembler/diff.html               --><!--                                     --><!--  (C) Copyright 2001 Richard Murray  --><!--  Designed by Richard Murray         --><!--  rmurray@heyrick.co.uk              --><!--                                     --><body bgcolor="#f0f0f0" text="#000000" link="#0022dd" vlink="#002288"><table border = "0" width="100%">  <tr>    <td align=center width=100>      <img src="arm3.gif" width=79 height=78 align = middle>    </td>    <td>      <h1 align="center"><font color="#800080">Processor<br>differences</font></h1>    </td>    <td align=center width=100>      <img src="arm3.gif" width=79 height=78 align = middle>    </td></table><p>&nbsp;<p>This assembler programming site deals with the older ARM processors - the ARM 2 and the ARM 3.Well written code should work on later ARM processors, including the StrongARM.<p><ul>  <li> ARM 2<br>       The processor within the first RISC OS machines. For a brief time the ARM 2 also powered       Arthur; but in the words of <i>STEPS</i>, that one is Better Best Forgotten. :-)</ul><p><ul>  <li> Next came the ARM 3<br>       This processor greatly boosted the behaviour of RISC OS due to a 4K cache.<br>       An extra opcode was added, <code>SWP</code> which swaps between registers and memory.<br>       Additionally, co-processor register 15 is used to communicate with the processor for       things such as reading its version number.</ul><p><ul>  <li> ARM 250<br>       This was created for the A30x0 series. The actual chip contains the entire ARM chipset       in one package (MEMC, VIDC, IOC, and ARM).<br>       The ARM within this package is an ARM 250. It is a version of the ARM 3 without the       co-processor register or the cache. It was designed to be cheap, the A30x0 series       being to the Archimedes like the Electron was to the BBC micro.</ul><p>To determine which processor you have, you need to conduct a few tests:<br><pre>  Does it understand SWP?    If not, it is an ARM 2  Does it understand CP15 instructions?    If not, it is an ARM 250.  It is an ARM 3.</pre>This method will probably fail on later processors. I do not have data on how to identifyprocessors later than the ARM 3.<br>Of course, you can make some assumptions about the processor based on the OS:<ul>  <li> If the ARM3Support module is present, an ARM 3 processor is in use...<br>       <code>Set Arm3$Present Yes<br>       RMEnsure ARM3Support 0.00 Set ARM3$Present No</code></ul><p>Here is some code to determine the processor type:<pre>REM Processor typeREMREM by Richard Murray 26th April 1999REM Updated 07/03/2001 so it won't kill 32-bit systems.REMREM Downloaded from: http://www.heyrick.co.uk/assembler/DIM code% 256FOR loop% = 0 TO 2 STEP 2  P% = code%  [ OPT loop%    STMFD   R13!, {R1-R12, R14}              ; Preserve registers    MOV     R0, #1                           ; Set up a handler for    ADR     R1, unknown_instruction          ; unknown instructions    MOV     R2, #0    MOV     R3, #0    SWI     &quot;OS_ChangeEnvironment&quot;    SWI     &quot;OS_EnterOS&quot;                     ; Enter SVC mode    MOV     R0, #2    \ Test for ARM 250 or better.    ADR     R2, safe_word                    ; Make R2 point somewhere safe    EQUD    &amp;E1021091                        ; &quot;SWP R1, R1, [R2]&quot;    MOV     R0, #250    \ Test for ARM 3.    CMP     R0, #250                         ; Compare R0 with 250.    EQUD    &amp;EE101F10                        ; &quot;MRCEQ CP15, 0, R1, C0, C0&quot;    MOV     R0, #3    TSTP    PC, #&amp;F0000000                   ; Return to USR mode.    MOV     R0, R0    LDMFD   R13!, {R1-R12, PC}               ; Restore registers and exit.  .unknown_instruction    ADDS    PC, R14, #4                      ; Upon unknown instruction, skip                                             ; PC on beyond the MOV instruction.  .safe_word    EQUD    0  ]NEXTa% = USR(code%)CASE a% OF  WHEN   2 : PRINT &quot;Running on an ARM 2&quot;  WHEN 250 : PRINT &quot;Running on an ARM 250&quot;  WHEN   3 : PRINT &quot;Running on an ARM 3&quot;OTHERWISE  : PRINT &quot;Running on unknown processor (reply = &quot;+STR$(a%)+&quot;)&quot;ENDCASEEND</pre><div align = right><a href="sw/proctype.basic"><i>Download example: proctype.basic</i></a></div><p>This software has only been tested on an ARM 3 processor.<p><hr size = "3"><a href="index.html#03">Return to assembler index</a><hr size = "3"><address>Copyright &copy; 2001 Richard Murray</address></body></html>

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