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<!doctype html public "-//W3C//DTD HTML 3.2//EN"><html><head><title>Memory Management</title><meta http-equiv="content-type" content="text/html; charset=ISO-8859-1" /><meta http-equiv="content-language" content="en" /><meta name="resource-type" content="document"><meta name="copyright" content="This document copyright 2001 by Richard Murray. Use for non-profit and education purposes explicitly granted."><meta name="author" content="Richard Murray"><meta name="rating" content="general"></head><!-- /assembler/memmng.html --><!-- --><!-- (C) Copyright 2001 Richard Murray --><!-- Designed by Richard Murray --><!-- rmurray@heyrick.co.uk --><!-- --><body bgcolor="#f0f0f0" text="#000000" link="#0022dd" vlink="#002288"><table border = "0" width="100%"> <tr> <td align=center width=100> <img src="arm3.gif" width=79 height=78 align = middle> </td> <td> <h1 align="center"><font color="#800080">Memory Management</font></h1> </td> <td align=center width=100> <img src="arm3.gif" width=79 height=78 align = middle> </td></table><p> <p><h2>Introduction</h2>The RISC OS machines work with two different types of memory - <i>logical</i> and<i>physical</i>.<br>The logical memory is the memory as seen by the OS, and the programmer. Your application beginsat &8000 and continues until &xxxxx.<br>The physical memory is the actual memory in the machine.<p>Under RISC OS, memory is broken into pages. Older machines have a page of 8/16/32K (depending oninstalled memory), and newer machines have a fixed 4K page. If you were to examine the pages inyour application workspace, you would most likely see that the pages were seemingly random, notin order. The pages relate to physical memory, combined to provide you with xxxx bytes of logicalmemory. The memory controller is constantly shuffling memory around so that each task that comesinto operation 'believes' it is loaded at &8000. Write a little application to count howmany wimp polls occur every second, you'll begin to appreciate how much is going on in thebackground.<p> <p><h2>MEMC : Older systems</h2>In ARM 2, 250, and 3 machines; the memory is controlled by the MEMC (MEMory Controller). Thisunit can cope with an address space of 64Mb, but in reality can only access 4Mb of physicalmemory. The 64Mb space is split into three sections:<pre> 0Mb - 32Mb : Logical RAM 32Mb - 48Mb : Physical RAM 48Mb - 64Mb : System ROMs and I/O</pre>Parts of the system ROMs and I/O are mapped over each other, so reading from it gives you codefrom ROM, and writing to it updates things like the VIDC (video/sound).<p>It is possible to fit up to 16Mb of memory to an older machine, but you will need a matched MEMCfor each 4Mb. People have reported that simply fitting two MEMCs (to give 8Mb) is either hairyor unreliable, or both. In practice, the hardware to do this properly only really existed forthe A540 machine, where each 4Mb was a slot-in memory card with an on-board MEMC. Other solutionsfor, say, the A5000 and the A410, are elaborate bodges. Look at<a href="http://www.castle.org.uk/castle/upg25.htm">http://www.castle.org.uk/castle/upg25.htm</a><font color = "red" size = "-1">[EXTERNAL LINK]</font> for an example of what is required to fit 8Mb into an A5000!<p>The MEMC is capable of restricting access to pages of memory in certain ways, either completeaccess, no access, no access in USR mode, or read-only access. Older versions of RISC OS onlyimplemented this loosely, so you need to be in SVC mode to access hardware directly but you couldquite easily trample over memory used by other applications.<p> <p><h2>MMU : Newer systems</h2>The newer systems, with ARM6 or later processor, have an MMU built into the processor. Thisconsists of the translation look-aside buffer (TLB), access control logic, and translation tablewalk logic. The MMU supports memory accesses based upon 1Mb sections or 4K pages. The MMU alsoprovides support for up to 16 'domains', areas of memory with specific access rights.<br>The TLB caches 64 translated entries. If the entry is for a virtual address, the control logicdetermines if access is permitted. If it is, the MMU outputs the appropriate physical addressotherwise is signals the processor to abort.<br>If the TLB misses (it doesn't contain an entry for the virtual address), the walk logic willretrieve the translation information from the (full) translation table in physical memory.<br>If the MMU should be disabled, the virtual address is output directly as the physical address.<p>It gets a lot more complicated, suffice to say that more access rights are possible and you canspecify memory to be bufferable and/or cacheable (or not), and the page size is fixed to 4K. Anormal RiscPC offers two banks of RAM, and is capable of addressing up to 256Mb of RAM in fairlystandard PC-style SIMMs, plus up to 2Mb of VRAM double-ported with the VIDC, plus hardware/ROMaddressing.<p>On the RiscPC, the maximum address space of an application is 28Mb. This is <i>not</i> arestriction of the MMU but a restriction in the 26-bit processor mode used by RISC OS. A 32-bitprocessor mode could, in theory, allocate the entire 256K to a single task.<br>All current versions of RISC OS are 26-bit.<p> <p><h2>System limitations</h2>Consider a RiscPC with an ARM610 processor.<br>The cache is 4K.<br>The bus speed is 16MHz (note, only slightly faster than the A5000!), and the hardware does notsupport burst-mode for memory accesses.<br>Upon a context switch (ie, making an application 'active') you need to remap it's memory to beginat &8000 and flush the cache.<br>I'll leave you to do the maths. <tt>:-)</tt><p> <p><hr size = 3><a href="index.html#03">Return to assembler index</a><hr size = 3><address>Copyright © 2001 Richard Murray</address></body></html>⌨️ 快捷键说明
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