32bit.html

关于ARM汇编的非常好的教程

       using external logic such as a memory management unit to generate an abort if the 64Mbyte
       range is exceeded, and converting that abort into an `address exception trap' for the
       application.
       <br>&nbsp;<br>

  <li> The new instructions to transfer data between general registers and the program status
       registers remain operative. The new instructions can be used by the operating system to
       return to a 32 bit mode after calling a binary containing code written for a 26 bit ARM.
       <br>&nbsp;<br>

  <li> When in a 32 bit program and data space configuration, all exceptions (including Undefined
       Instruction and Software Interrupt) return the processor to a 32 bit mode, so the
       operating system must be modified to handle them.
       <br>&nbsp;<br>

  <li> If the processor attempts to write to a location between &0 and &1F inclusive (i.e. the
       exception vectors), hardware prevents the write operation and generates a data abort.
       This allows the operating system to intercept all changes to the exception vectors and
       redirect the vector to some veneer code. The veneer code should place the processor in a
       26 bit mode before calling the 26 bit exception handler.
</ul>

In all other respects, when operating in a 26 bit mode the ARM behaves as like a 26 bit ARM. The
relevant bits of the CPSR appear to be incorporated back into R15 to form the PC/PSR with the I
and F bits in bits 27 and 26. The instruction set behaves like that of the ARM2aS macrocell,
with the addition of the MRS and MSR instructions.
<p>&nbsp;<p>


The registers available on the ARM 6 (and later) in 32 bit mode are:

<pre>

User26   SVC26    IRQ26    FIQ26      User     SVC      IRQ      ABT      UND      FIQ

R0 ----- R0 ----- R0 ----- R0 --   -- R0 ----- R0 ----- R0 ----- R0 ----- R0 ----- R1
R1 ----- R1 ----- R1 ----- R1 --   -- R1 ----- R1 ----- R1 ----- R1 ----- R1 ----- R2
R2 ----- R2 ----- R2 ----- R2 --   -- R2 ----- R2 ----- R2 ----- R2 ----- R2 ----- R2
R3 ----- R3 ----- R3 ----- R3 --   -- R3 ----- R3 ----- R3 ----- R3 ----- R3 ----- R3
R4 ----- R4 ----- R4 ----- R4 --   -- R4 ----- R4 ----- R4 ----- R4 ----- R4 ----- R4
R5 ----- R5 ----- R5 ----- R5 --   -- R5 ----- R5 ----- R5 ----- R5 ----- R5 ----- R5
R6 ----- R6 ----- R6 ----- R6 --   -- R6 ----- R6 ----- R6 ----- R6 ----- R6 ----- R6
R7 ----- R7 ----- R7 ----- R7 --   -- R7 ----- R7 ----- R7 ----- R7 ----- R7 ----- R7
R8 ----- R8 ----- R8       R8_fiq     R8 ----- R8 ----- R8 ----- R8 ----- R8       R8_fiq
R9 ----- R9 ----- R9       R9_fiq     R9 ----- R9 ----- R9 ----- R9 ----- R9       R9_fiq
R10 ---- R10 ---- R10      R10_fiq    R10 ---- R10 ---- R10 ---- R10 ---- R10      R10_fiq
R11 ---- R11 ---- R11      R11_fiq    R11 ---- R11 ---- R11 ---- R11 ---- R11      R11_fiq
R12 ---- R12 ---- R12      R12_fiq    R12 ---- R12 ---- R12 ---- R12 ---- R12      R12_fiq
R13      R13_svc  R13_irq  R13_fiq    R13      R13_svc  R13_irq  R13_abt  R13_und  R13_fiq
R14      R14_svc  R14_irq  R14_fiq    R14      R14_svc  R14_irq  R14_abt  R14_und  R14_fiq
--------- R15 (PC / PSR) ---------    --------------------- R15 (PC) ---------------------
                                      ----------------------- CPSR -----------------------
                                               SPSR_svc SPSR_irq SPSR_abt SPSR_und SPSR_fiq
</pre>

In short, the 32 bit differences are:
<ul>
  <li> The PC is a full 32 bits wide, and used singularly as a Program Counter.
       <br>&nbsp;<br>

  <li> The PSR is contained within its own register, the CPSR.
       <br>&nbsp;<br>

  <li> Each privileged mode has a private SPSR register in which to save the CPSR.
       <br>&nbsp;<br>

  <li> There are two new privileged modes, each of which has private copies of R13 and R14.
</ul>
<p>&nbsp;<p>


<h2>The CPSR and SPSR registers</h2>

The allocation of the bits within the CPSR (and the SPSR registers to which it is saved) is:

<pre>
  31 30 29 28  ---   7   6   -   4   3   2   1   0
  N  Z  C  V         I   F       M4  M3  M2  M1  M0

                                 0   0   0   0   0     User26 mode
                                 0   0   0   0   1     FIQ26 mode
                                 0   0   0   1   0     IRQ26 mode
                                 0   0   0   1   1     SVC26 mode
                                 1   0   0   0   0     User mode
                                 1   0   0   0   1     FIQ mode
                                 1   0   0   1   0     IRQ mode
                                 1   0   0   1   1     SVC mode
                                 1   0   1   1   1     ABT mode
                                 1   1   0   1   1     UND mode
</pre>

Please refer to <a href="psr.html">the (26 bit) PSR</a> for information on the N, Z, C, V flags
and the I and F interrupt flags.
<p>&nbsp;<p>


<h2>So what does it mean in practice?</h2>

Most ARM code will work correctly. The only things that will not work are any operations which
fiddle with R15 to set the processor status. Unfortunately, this isn't as easy to fix as it
seems.<br>
I examined a 9K program (a MODE 7 teletext frame viewer, written in C) for potential problems,
basically looking for:
<ul>
  <li> A <code>MOVS</code> with R15 as the destination.
  <li> Any <code>LDMFD</code> suffixed with the '^' character <i>and</i> loading R15.
</ul>

About 64 instructions fell into one of these categories.
<p>

There is likely to be few ways to make the conversion process automatic. Basically...
<ul>
  <li> How will the system know what is data, and what is code.<br>
       Actually, a clever rules-based program should be able to make a fairly good guess, but is
       a &quot;<i>fairly good guess</i>&quot; good enough?
  <li> There is NO simple instruction replacement. An automatic system probably could patch in
       the required instructions and jiggle the code around, but this could cause unexpected side
       effects, like an ADR directive no longer being in range.
  <li> It is incredibly hacky. Surely, much better to recompile, or to repair the source code.
</ul>
<p>&nbsp;<p>


It is <i>NOT</i> easy. Such a small change, but with such far-reaching consequences.
<p>&nbsp;<p>


In <i>comp.sys.acorn.programmer</i>, Stewart Brodie answered my query with a hint that may be
useful to people intending to work with 32 bit code:
<pre><font color="navy">> How is it possible, if 32 bit code uses MSR/MRS to transfer status and
> register, and older ARMs don't have those instructions?
> Are we into "black magic" code for this?</font>

You take advantage of the fact that the encodings for MSR and MRS act as NOPs
on ARM2 and ARM3 ;-)  With some careful arrangement, you can write fairly
tight code.

To refer back to earlier postings, an example of when MOVS pc, lr in a
32-bit mode is useful (entered in SVC or IRQ mode, IRQs disabled):

        ADR     r14, CallBackRegs
        TEQ     PC,PC
        LDREQ   r0, [r14, #16*4]    ; The CPSR
        MSREQ   SPSR_cxsf, r0       ; put into SPSR_svc/SPSR_irq ready for MOVS
        LDMIA   r14, {r0-r14}^      ; Restore user registers
        NOP
        LDR     r14, [r14, #15*4]   ; The pc
        MOVS    pc, r14             ; Back we go (32-bit safe - SPSR set up)

(CallBackRegs contains user mode registers: R0-R15, plus the CPSR if in a
32-bit mode)
</pre>
<p>&nbsp;<p>&nbsp;<p>


<div align = right><a href="sw/scan32bit.zip"><i>Download a 32 bit code scanner (12K)</i></a></div>
<p>&nbsp;<p>&nbsp;<p>


<h2>Where is the example?</h2>

In the logical place, in the document describing the <a href="psr.html">processor status
register</a>...
<p>&nbsp;<p>&nbsp;<p>



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<address>Copyright &copy; 2001 Richard Murray</address>
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