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<!doctype html public "-//W3C//DTD HTML 3.2//EN"><html><head><title>32 bit operation</title><meta http-equiv="content-type" content="text/html; charset=ISO-8859-1" /><meta http-equiv="content-language" content="en" /><meta name="resource-type" content="document"><meta name="copyright" content="This document copyright 2001 by Richard Murray. Use for non-profit and education purposes explicitly granted."><meta name="author" content="Richard Murray"><meta name="rating" content="general"></head><!-- /assembler/32bit.html --><!-- --><!-- (C) Copyright 2001 Richard Murray --><!-- Designed by Richard Murray --><!-- rmurray@heyrick.co.uk --><!-- --><body bgcolor="#f0f0f0" text="#000000" link="#0022dd" vlink="#002288"><table border = "0" width="100%"> <tr> <td align=center width=100> <img src="arm3.gif" width=79 height=78 align = middle> </td> <td> <h1 align="center"><font color="#800080">32 bit operation</font></h1> </td> <td align=center width=100> <img src="arm3.gif" width=79 height=78 align = middle> </td></table><p> <p><i>A lot of this information is taken from the ARM assembler manual. I didn't have a 32 bitprocessor at the time, so trusted the documentation...<br>As it happens, the documentation erroneously stated that UMUL and UMLA could <u>only</u> beperformed in 32bit mode. Well, that is incorrect, if your processor can do it (ie: StrongARM), itwill work in 32bit OR 26bit...</i><p> <p>The ARM2 and ARM3 have a 32 bit data bus and a 26 bit address bus. On later versions of the ARM,both the data bus and the address bus are a full 32 bits wide.<br>This explains how a "32 bit processor" can be referred to as 26 bit. The data width andinstruction/word size is 32 bit, and always has been, but the address bus is only 24 bit.<br>Oh, whoops, I said 26 bit, didn't I?<br><tt>:-)</tt> Well, as PC is <i>always</i> word aligned, the lower two bits will always be zero inan address, so on the ARM2/ARM3 processor these bits hold the processor mode setting. The widthof PC is, effectively, 26 bit even though only 24 bits are actually used.<p>This is no a problem on the older machines. 4Mb memory was the norm. Some people upgraded to 8Mb,and 16Mb was the theoretical limit.<br>However a RiscPC with a 26 bit program counter would not have been possible, as 26 bits onlyallows you to address %11111111111111111111111100 (or 67108860 bytes, or 64Mb). The RiscPCallows for 258Mb of memory to be installed.<br>This, incidentally, explains the 28Mb size limit for application tasks; the system is expected tobe compatible with the older RISC OS API.<p>The majority of the assembler site has been written regarding 26 bit mode of operation, which iscompatible with the versions of RISC OS currently available (ie, RISC OS 2 to RISC OS 4); thoughsome parts cover 32 bit modes (one example briefly runs in SVC32!), and I have noted parts of theexamples that are 32 bit unfriendly.<p>Those with a RiscPC, Mico, RiscStation, A7000 etc have the ability to run a fully 32 bitoperating system; indeed ARMLinux is such an operating system. RISC OS is not, because RISC OSneeds, for the moment, to remain compatible with existing versions. It is the old dichotomy. Itis wonderful to have a nice shiny new fully 32 bit version of RISC OS, but not so good when yourealise a lot of your must-have software won't so much as load!<br>RISC OS isn't totally 26 bit. Some of the handlers need to work in 32 bit mode; however it is limited by money (ie, who's going to pay for RISC OS to be fully converted; and who's going topay for new development tools to rebuild their code (PD software is strong on RISC OS)) and alsoby necessity (ie, lots of people use Impression but CC is no longer with us; it is quite likelyImpression won't work on an updated RISC OS, so people will not see a necessity to upgrade iftheir desired software won't work).<p> <p>Why is this even an issue?<br>Newer ARM processors will not support 26 bit operation. Several hybrids were made (ARM6, ARM7,StrongARM), but time has come to draw the line. You can either add the complexity of a 26/32 bitsystem, or you can go 32 bit only and have a simpler, smaller processor.<br>Either we go with the flow, or get left behind... So really, this <i>is</i> an issue, and wedon't have a choice.<p> <p><h2>32 bit architecture</h2>The ARM architecture changed significantly with the introduction of the ARM6 series. Below, weshall describe the differences in behaviour between 26 bit and 32 bit operation.<p>In the ARM 6, the program counter was extended to a full 32 bits. As a result:<ul> <li> The PSR had to be separated from the PC into its own register, the CPSR (Current Program Status Register). <br> <br> <li> The PSR can no longer be saved with the PC when changing processor modes;<br> instead, each privileged mode now has an extra register - the SPSR (Saved Program Status Register) - to hold the previous mode's PSR. <br> <br> <li> Instructions have been added to use these new status registers.</ul>A further change was the addition of extra privileged processor modes, allowed by the PSR nowhaving a full 32 bits to use. These modes are used to handle Undefined instruction and Abortexceptions. Consequently:<ul> <li> Undefined instructions, aborts, and supervisor code no longer have to share the same mode. This has removed restrictions on Supervisor mode programs which existed on earlier ARMs. <li> The availability of these features in the ARM6 series (and other later compatible chips) is set by one of several on-chip control registers. One of three processor configurations can be selected: <ul> <li> 26 bit program and data space. This configuration forces ARM to operate with a 26 bit address space. In this configuration only the four 26 bit modes are available (refer to the <a href="regs.html">Processor modes description</a>); it is impossible to select a 32 bit mode.<br> This configuration is set at reset on all current ARM6 and 7 series processors. <br> <br> <li> 26 bit program space and 32 bit data space. This is the same as the 26 bit program and data space configuration, except that address exceptions are disabled to allow data transfer operations to access the full 32 bit address space. <br> <br> <li> 32 bit program and data space. This configuration extends the address space to 32 bits, and introduces major changes to the programmer's model. In this configuration you can select any of the 26 bit and the 32 bit processor modes (see Processor modes below). </ul></ul><p> <p>When configured for a 32 bit program and data space, the ARM6 and ARM7 series support tenoverlapping processor modes of operation:<ul> <li> User mode: the normal program execution state<br> <i>or</i> User26 mode: a 26 bit version <br> <br> <li> FIQ mode: designed to support a data transfer or channel process<br> <i>or</i> FIQ26 mode: a 26 bit version <br> <br> <li> IRQ mode: used for general purpose interrupt handling<br> <i>or</i> IRQ26 mode: a 26 bit version <br> <br> <li> SVC mode: a protected mode for the operating system<br> <i>or</i> SVC26 mode: a 26 bit version <br> <br> <li> Abort mode (abbreviated to ABT mode): entered after a data or instruction prefetch abort <br> <br> <li> Undefined mode (abbreviated to UND mode): entered when an undefined instruction is executed.</ul>When in a 26 bit processor mode, the programmer's model reverts to that of earlier 26 bit ARMprocessors. The behaviour is the same as that of the ARM2aS macrocell with the followingalterations:<ul> <li> Address exceptions are only generated by ARM when it is configured for 26 bit program and data space.<br> In other configurations the OS may still simulate the behaviour of address exception,⌨️ 快捷键说明
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