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<!doctype html public "-//W3C//DTD HTML 3.2//EN"><html><head><title>Floating point instructions</title><meta http-equiv="content-type" content="text/html; charset=ISO-8859-1" /><meta http-equiv="content-language" content="en" /><meta name="resource-type" content="document"><meta name="copyright" content="This document copyright 2001 by Richard Murray. Use for non-profit and education purposes explicitly granted."><meta name="author" content="Richard Murray"><meta name="rating" content="general"></head><!-- /assembler/fpops.html --><!-- --><!-- (C) Copyright 2000 Richard Murray --><!-- Designed by Richard Murray --><!-- rmurray@heyrick.co.uk --><!-- --><body bgcolor="#f0f0f0" text="#000000" link="#0022dd" vlink="#002288"><table border = "0" width="100%"> <tr> <td align=center width=100> <img src="arm3.gif" width=79 height=78 align = middle> </td> <td> <h1 align="center"><font color="#800080">Floating point<br>instructions</font></h1> </td> <td align=center width=100> <img src="arm3.gif" width=79 height=78 align = middle> </td></table><p> <p>The BASIC assembler, as standard, does not have any support for true floating point instructions.You have the ability to convert integers to your implementation-defined 'floating point' andperform basic mathematics with them (most usually fixed point), but you cannot interact with afloating point co-processor and do things the 'native' way.<br>There are, however, patches which extend the things that the assembler can do - which includeFP instructions.<p>Parts of this documentation has been taken from the ARM Assembler manual.<p> <p> <p>The ARM processor can interface with up to sixteen co-processors. The ARM3 and later have virtualco-processors within the ARM to handle internal control functions. But the first co-processorthat was available was the floating point processor. This chip handles floating point maths tothe IEEE standard.<br>A standard ARM floating point instruction set has been defined, so that the code may be usedacross all RISC OS machines. If the actual hardware does not exist, then the instructions aretrapped and executed by the floating point emulator module (FPEmulator). The program does notneed to know whether or not the FP co-processor is present. The only real difference will bespeed of execution.<p>The ARM IEEE FP system has eight high precision FP registers (F0 to F7). The register format isirrelevant as you cannot access those registers directly, the register is only 'visible' when itis transferred to memory or to an ARM register. In memory, an FP register consumes threewords, but as the FP system will be reloading its own register, the format of these three wordsis considered irrelevant.<br>There is also an FPSR (floating point status register) which, similar to the ARM's own PSR,holds the status information that an application might require. Each of the flags available hasa 'trap' which allows the application to enable or disable traps associated with the givenerror.<br>The FPSR also allows you to tell between different implementations of the FP system.<br>There may also be an FPCR (floating point control register). This holds information that theapplication should not access, such as flags to turn the FP unit on and off. Typically, hardwarewill have an FPCR, software will not.<p>FP units can be software implementations such as the FPEmulator modules, hardware implementationssuch as the FP chip (and support code), or a combination of both.<br>The best example of a 'both' that I can think of is the Warm Silence Software patch that willutilise the 80x87 chip on suitably equipped PC co-processor cards as a floating point processorfor ARM FP operations. Talk about resource sharing...!<p>The results are calculated as though it were infinite precision, then they are rounded to thelength required. The rounding may be to nearest, to +infinity(P), to -infinity(M), or to zero.The default is rounding to nearest. If a tie, it will round to nearest even.<br>The working precision is 80 bits, comprising of a 64 bit mantissa, a 15 bit exponent, and a signbit. Specific instructions that work with single precision may provide better performance insome implementations - notably fully-software-based ones.<p>The FPSR contains the necessary status for the FP system. The IEEE flags are always present, butthe result flags are only available after an FP compare operation.<p><i>Floating point instructions should not be used from SVC mode.</i><p>Exception Flags Byte, the lower byte of the FPSR.<pre> 6 4 3 2 1 0FPSR: Reserved INX UFL OFL DVZ IVO</pre>Whenever an exception condition arises, the appropriate cumulative exception flag in bits 0 to 4will be set to 1. If the relevant trap enable bit is set, then an exception is also delivered tothe user's program in a manner specific to the operating system. (Note that in the case ofunderflow, the state of the trap enable bit determines under which conditions the underflow flagwill be set.) These flags can only be cleared by a WFS instruction.<p><code>IVO - invalid operation</code><br>The IVO flag is set when an operand is invalid for the operation to be performed. Invalidoperations are:<ul> <li> Any operation on a trapping NaN (not-a-number) <li> Magnitude subtraction of infinities, eg + + - <li> Multiplication of 0 by 0 <li> Division of 0/0 or x/0 <li> x REM y where x = 8 or y = 0<br> (REM is the `remainder after floating point division' operator.) <li> Square root of any number < 0 (but (-0) = -0) <li> Conversion to integer or decimal when overflow, or a NaN operand make it impossible<br> If overflow makes a conversion to integer impossible, then the largest positive or negative integer is produced (depending on the sign of the operand) and IVO is signalled <li> Comparison with exceptions of Unordered operands <li> ACS, ASN, SIN, COS, TAN, LOG, LGN, POW, or RPW with invalid/incorrect arguments.</ul><p><code>DVZ - division by zero</code><br>The DVZ flag is set if the divisor is zero and the dividend a finite, non-zero number. Acorrectly signed infinity is returned if the trap is disabled. The flag is also set for LOG(0)and for LGN(0). Negative infinity is returned if the trap is disabled.<p><code>OFL - overflow</code><br>The OFL flag is set whenever the destination format's largest number is exceeded in magnitude bywhat the rounded result would have been were the exponent range unbounded. As overflow isdetected after rounding a result, whether overflow occurs or not after some operations dependson the rounding mode.<br>If the trap is disabled either a correctly signed infinity is returned, or the format's largestfinite number. This depends on the rounding mode and floating point system used.<p><code>UFL - underflow</code><br>Two correlated events contribute to underflow:<ul> <li> Tininess - the creation of a tiny non-zero result smaller in magnitude than the format's smallest normalised number. <li> Loss of accuracy - a loss of accuracy due to denormalisation that may be greater than would be caused by rounding alone.</ul>The UFL flag is set in different ways depending on the value of the UFL trap enable bit. If thetrap is enabled, then the UFL flag is set when tininess is detected regardless of loss ofaccuracy. If the trap is disabled, then the UFL flag is set when both tininess and loss ofaccuracy are detected (in which case the INX flag is also set); otherwise a correctly signedzero is returned.<br>As underflow is detected after rounding a result, whether underflow occurs or not after someoperations depends on the rounding mode.<p><code>INX - inexact</code><br>The INX flag is set if the rounded result of an operation is not exact (different from the value computable with infinite precision), or overflow has occurred while the OFL trap wasdisabled, or underflow has occurred while the UFL trap was disabled. OFL or UFL traps takeprecedence over INX.<br>The INX flag is also set when computing SIN or COS, with the exceptions of SIN(0) and COS(1).<br>The old FPE and the FPPC system may differ in their handling of the INX flag. Because of thisinconsistency we recommend that you do not enable the INX trap.<p> <p>Precision is:<ul> <li> <code>S -</code> single <li> <code>D -</code> double <li> <code>E -</code> double extended <li> <code>P -</code> packed decimal <li> <code>EP -</code> extended packed decimal</ul><p> <p>Rounding modes are:<ul> <li> <code> -</code> nearest (no letter required) <li> <code>P -</code> plus infinity <li> <code>M -</code> minus infinity <li> <code>Z -</code> zero</ul><p> <p><a name="ldf"></a><br><code>LDF<condition><precision><fp register>, <address></code><br>Load Floating Point value<br>The address can be in the forms:<ul> <li> [Rn] <li> [Rn], #offset <li> [Rn, #offset] <li> [Rn, #offset]!</ul>This call is similar to LDR.<br>Your assembler may allow literals to be used, such as LDFS F0, [float_value]<p> <p><a name="stf"></a><br><code>STF<condition><precision><fp register>, <address></code><br>Store floating point value.The address can be in the forms:<ul> <li> [Rn] <li> [Rn], #offset <li> [Rn, #offset] <li> [Rn, #offset]!</ul>This call is similar to STR.<br>Your assembler may allow literals to be used, such as STFED F0, [float_value]<p> <p><a name="lfm"></a><a name="sfm"></a><br><code>LFM</code> and <code>SFM</code><br>These are similar in idea to LDM and STM, but they will not be described because some versionsof FPEmulator do not support them. The FP module in RISC OS 3.1x (2.87) does, as do (I think)later versions. If you know they your software will only operate on a system that supports SFM,then use it. Otherwise you'll need to 'fake' it with a sequence of STFs. Likewise for LFM/LDF.<p> <p><a name="flt"></a><br><code>FLT<condition><precision><rounding> <fp register>, <register><br>FLT<condition><precision><rounding> <fp register>, #<value></code><br>Convert integer to floating point, either an ARM register or an absolute value.<p> <p><a name="fix"></a><br><code>FIX<condition><rounding> <register>, <fp register></code><br>Convert floating point to integer.<p> <p><a name="wfs"></a><br><code>WFS<condition> <register></code><br>Write floating point status register with the contents of the ARM register specified.<p> <p><a name="rfs"></a><br><code>RFS<condition> <register></code><br>Read floating point status register into the ARM register specified.<p> <p><a name="wfc"></a><br><code>WFC<condition> <register></code><br>Write floating point control register with the contents of the ARM register specified.<br>Supervisor mode only, and only on hardware that supports it.<p> <p><a name="rfc"></a><br><code>RFC<condition> <register></code><br>Read floating point control register into the ARM register specified.<br>Supervisor mode only, and only on hardware that supports it.<p> <p>Floating point coprocessor data operations:<br>The formats of these instructions are:<br><ul> <li> binary_operation condition precision rounding Fdest, Fsource, Fsource <li> binary_operation condition precision rounding Fdest, Fdest, #value <li> unary_operation condition precision rounding Fdest, Fsource <li> unary_operation condition precision rounding Fdest, #value</ul>The #value constants should be 0, 1, 2, 3, 4, 5, 10, or 0.5.⌨️ 快捷键说明
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