📄 lcd.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity lcd is
port(DP1,DP2,DP3 : in std_logic; --78E58的A8,A9,A10
RS,CS1,CS2 : out std_logic;
LCDE : out std_logic;
RW : out std_logic);
end lcd ;--
---
architecture hav of lcd is
begin
process(DP1,DP2,DP3)
begin
if( DP1='0' and DP2='0' and DP3='0') then --选种1区,读状态
lcde<='1';rs<='0';rw<='1';cs1<='1';cs2<='0';
elsif(DP1='0' and DP2='0' and DP3='1')then --选种1区,写指令
lcde<='1';rs<='0';rw<='0';cs1<='1';cs2<='0';
elsif(DP1='0' and DP2='1' and DP3='0')then --禁止使用
lcde<='0';rs<='1';rw<='1';cs1<='1';cs2<='0';
elsif(DP1='0' and DP2='1' and DP3='1')then --选种1区,写数据
lcde<='1';rs<='1';rw<='0';cs1<='1';cs2<='0';
elsif(DP1='1' and DP2='0' and DP3='0')then --选种2区,读状态
lcde<='1';rs<='0';rw<='1';cs1<='0';cs2<='1';
elsif(DP1='1' and DP2='0' and DP3='1')then --选种2区,写指令
lcde<='1';rs<='0';rw<='0';cs1<='0';cs2<='1';
elsif(DP1='1' and DP2='1' and DP3='0')then --禁止使用
lcde<='0';rs<='1';rw<='1';cs1<='0';cs2<='1';
elsif(DP1='1' and DP2='1' and DP3='1')then --选种2区,写数据
lcde<='1';rs<='1';rw<='0';cs1<='0';cs2<='1';
else
lcde<='0';rs<='1';rw<='1';cs1<='0';cs2<='0'; --禁止使用
end if;
end process;
end hav;
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