📄 lines.rpt
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-- Node name is ':54' = 'c2'
-- Equation name is 'c2', location is LC102, type is buried.
c2 = DFFE( _EQ015 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = !b6 & b7 & !b8 & !en00 & !en01
# c2 & en00
# c2 & en01;
-- Node name is ':55' = 'c3'
-- Equation name is 'c3', location is LC111, type is buried.
c3 = DFFE( _EQ016 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = b6 & b7 & !b8 & !en00 & !en01
# c3 & en00
# c3 & en01;
-- Node name is ':56' = 'c4'
-- Equation name is 'c4', location is LC108, type is buried.
c4 = DFFE( _EQ017 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = !b6 & !b7 & b8 & !en00 & !en01
# c4 & en00
# c4 & en01;
-- Node name is ':57' = 'c5'
-- Equation name is 'c5', location is LC112, type is buried.
c5 = DFFE( _EQ018 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ018 = b6 & !b7 & b8 & !en00 & !en01
# c5 & en00
# c5 & en01;
-- Node name is ':58' = 'c6'
-- Equation name is 'c6', location is LC110, type is buried.
c6 = DFFE( _EQ019 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ019 = !b6 & b7 & b8 & !en00 & !en01
# c6 & en00
# c6 & en01;
-- Node name is ':59' = 'c7'
-- Equation name is 'c7', location is LC100, type is buried.
c7 = DFFE( _EQ020 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ020 = b6 & b7 & b8 & !en00 & !en01
# c7 & en00
# c7 & en01;
-- Node name is ':63' = 'd0'
-- Equation name is 'd0', location is LC098, type is buried.
d0 = DFFE( _EQ021 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ021 = d0 & en00
# d0 & en01;
-- Node name is ':64' = 'd1'
-- Equation name is 'd1', location is LC091, type is buried.
d1 = DFFE( _EQ022 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ022 = d1 & en00
# d1 & en01
# !b9 & !b10 & !b11 & !en00 & !en01;
-- Node name is ':65' = 'd2'
-- Equation name is 'd2', location is LC090, type is buried.
d2 = DFFE( _EQ023 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ023 = d2 & en00
# d2 & en01
# !b10 & !b11 & !en00 & !en01;
-- Node name is ':66' = 'd3'
-- Equation name is 'd3', location is LC081, type is buried.
d3 = DFFE( _EQ024 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ024 = !b10 & !b11 & !en00 & !en01
# !b9 & !b11 & !en00 & !en01
# d3 & en00
# d3 & en01;
-- Node name is ':67' = 'd4'
-- Equation name is 'd4', location is LC087, type is buried.
d4 = DFFE( _EQ025 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ025 = d4 & en00
# d4 & en01
# !b11 & !en00 & !en01;
-- Node name is ':68' = 'd5'
-- Equation name is 'd5', location is LC118, type is buried.
d5 = DFFE( _EQ026 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ026 = !b11 & !en00 & !en01
# !b9 & !b10 & !en00 & !en01
# d5 & en00
# d5 & en01;
-- Node name is ':69' = 'd6'
-- Equation name is 'd6', location is LC084, type is buried.
d6 = DFFE( _EQ027 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ027 = d6 & en00
# d6 & en01
# !b11 & !en00 & !en01
# !b10 & !en00 & !en01;
-- Node name is ':70' = 'd7'
-- Equation name is 'd7', location is LC126, type is buried.
d7 = DFFE( _EQ028 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ028 = !b11 & !en00 & !en01
# !b10 & !en00 & !en01
# !b9 & !en00 & !en01
# d7 & en00
# d7 & en01;
-- Node name is 'h1' = ':21'
-- Equation name is 'h1', type is output
h1 = DFFE( _EQ029 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ029 = c7 & !en00 & !en01
# en00 & h1
# en01 & h1;
-- Node name is 'h2' = ':23'
-- Equation name is 'h2', type is output
h2 = DFFE( _EQ030 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ030 = c6 & !en00 & !en01
# en00 & h2
# en01 & h2;
-- Node name is 'h3' = ':25'
-- Equation name is 'h3', type is output
h3 = DFFE( _EQ031 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ031 = c5 & !en00 & !en01
# en00 & h3
# en01 & h3;
-- Node name is 'h4' = ':27'
-- Equation name is 'h4', type is output
h4 = DFFE( _EQ032 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ032 = c4 & !en00 & !en01
# en00 & h4
# en01 & h4;
-- Node name is 'h5' = ':29'
-- Equation name is 'h5', type is output
h5 = DFFE( _EQ033 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ033 = c3 & !en00 & !en01
# en00 & h5
# en01 & h5;
-- Node name is 'h6' = ':31'
-- Equation name is 'h6', type is output
h6 = DFFE( _EQ034 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ034 = c2 & !en00 & !en01
# en00 & h6
# en01 & h6;
-- Node name is 'h7' = ':33'
-- Equation name is 'h7', type is output
h7 = DFFE( _EQ035 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ035 = c1 & !en00 & !en01
# en00 & h7
# en01 & h7;
-- Node name is 'h8' = ':35'
-- Equation name is 'h8', type is output
h8 = DFFE( _EQ036 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ036 = c0 & !en00 & !en01
# en00 & h8
# en01 & h8;
-- Node name is 'L1' = ':5'
-- Equation name is 'L1', type is output
L1 = DFFE( d7 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'L2' = ':7'
-- Equation name is 'L2', type is output
L2 = DFFE( d6 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'L3' = ':9'
-- Equation name is 'L3', type is output
L3 = DFFE( d5 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'L4' = ':11'
-- Equation name is 'L4', type is output
L4 = DFFE( d4 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'L5' = ':13'
-- Equation name is 'L5', type is output
L5 = DFFE( d3 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'L6' = ':15'
-- Equation name is 'L6', type is output
L6 = DFFE( d2 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'L7' = ':17'
-- Equation name is 'L7', type is output
L7 = DFFE( d1 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'L8' = ':19'
-- Equation name is 'L8', type is output
L8 = DFFE( d0 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information f:\display\lines.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 8,234K
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