📄 lines.rpt
字号:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\display\lines.rpt
lines
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+- LC65 L8
|
| Other LABs fed by signals
| that feed LAB 'E'
LC | | A B C D E F G H | Logic cells that feed LAB 'E':
Pin
83 -> - | - - - - - - - - | <-- clk
LC98 -> * | - - - - * - * - | <-- d0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\display\lines.rpt
lines
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+--------------------- LC86 h1
| +------------------- LC85 L2
| | +----------------- LC93 L4
| | | +--------------- LC94 L5
| | | | +------------- LC88 L6
| | | | | +----------- LC83 L7
| | | | | | +--------- LC91 d1
| | | | | | | +------- LC90 d2
| | | | | | | | +----- LC81 d3
| | | | | | | | | +--- LC87 d4
| | | | | | | | | | +- LC84 d6
| | | | | | | | | | |
| | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | that feed LAB 'F'
LC | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
LC86 -> * - - - - - - - - - - | - - - - - * - - | <-- h1
LC91 -> - - - - - * * - - - - | - - - - - * - - | <-- d1
LC90 -> - - - - * - - * - - - | - - - - - * - - | <-- d2
LC81 -> - - - * - - - - * - - | - - - - - * - - | <-- d3
LC87 -> - - * - - - - - - * - | - - - - - * - - | <-- d4
LC84 -> - * - - - - - - - - * | - - - - - * - - | <-- d6
Pin
83 -> - - - - - - - - - - - | - - - - - - - - | <-- clk
12 -> * - - - - - * * * * * | - - - - - * * * | <-- en00
11 -> * - - - - - * * * * * | - - - - - * * * | <-- en01
LC114-> - - - - - - * * * * * | - - - - - * - * | <-- b11
LC113-> - - - - - - * * * - * | - - - - - * - * | <-- b10
LC115-> - - - - - - * - * - - | - - - - - * - * | <-- b9
LC100-> * - - - - - - - - - - | - - - - - * * - | <-- c7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\display\lines.rpt
lines
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+------------------------------- LC109 h2
| +----------------------------- LC107 h3
| | +--------------------------- LC105 h4
| | | +------------------------- LC104 h5
| | | | +----------------------- LC101 h6
| | | | | +--------------------- LC99 h7
| | | | | | +------------------- LC97 h8
| | | | | | | +----------------- LC106 c0
| | | | | | | | +--------------- LC103 c1
| | | | | | | | | +------------- LC102 c2
| | | | | | | | | | +----------- LC111 c3
| | | | | | | | | | | +--------- LC108 c4
| | | | | | | | | | | | +------- LC112 c5
| | | | | | | | | | | | | +----- LC110 c6
| | | | | | | | | | | | | | +--- LC100 c7
| | | | | | | | | | | | | | | +- LC98 d0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'G'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
LC109-> * - - - - - - - - - - - - - - - | - - - - - - * - | <-- h2
LC107-> - * - - - - - - - - - - - - - - | - - - - - - * - | <-- h3
LC105-> - - * - - - - - - - - - - - - - | - - - - - - * - | <-- h4
LC104-> - - - * - - - - - - - - - - - - | - - - - - - * - | <-- h5
LC101-> - - - - * - - - - - - - - - - - | - - - - - - * - | <-- h6
LC99 -> - - - - - * - - - - - - - - - - | - - - - - - * - | <-- h7
LC97 -> - - - - - - * - - - - - - - - - | - - - - - - * - | <-- h8
LC106-> - - - - - - * * - - - - - - - - | - - - - - - * - | <-- c0
LC103-> - - - - - * - - * - - - - - - - | - - - - - - * - | <-- c1
LC102-> - - - - * - - - - * - - - - - - | - - - - - - * - | <-- c2
LC111-> - - - * - - - - - - * - - - - - | - - - - - - * - | <-- c3
LC108-> - - * - - - - - - - - * - - - - | - - - - - - * - | <-- c4
LC112-> - * - - - - - - - - - - * - - - | - - - - - - * - | <-- c5
LC110-> * - - - - - - - - - - - - * - - | - - - - - - * - | <-- c6
LC100-> - - - - - - - - - - - - - - * - | - - - - - * * - | <-- c7
LC98 -> - - - - - - - - - - - - - - - * | - - - - * - * - | <-- d0
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
12 -> * * * * * * * * * * * * * * * * | - - - - - * * * | <-- en00
11 -> * * * * * * * * * * * * * * * * | - - - - - * * * | <-- en01
LC116-> - - - - - - - * * * * * * * * - | - - - - - - * * | <-- b8
LC117-> - - - - - - - * * * * * * * * - | - - - - - - * * | <-- b7
LC122-> - - - - - - - * * * * * * * * - | - - - - - - * * | <-- b6
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\display\lines.rpt
lines
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------------------------------- LC120 L1
| +----------------------------- LC123 L3
| | +--------------------------- LC114 b11
| | | +------------------------- LC113 b10
| | | | +----------------------- LC115 b9
| | | | | +--------------------- LC116 b8
| | | | | | +------------------- LC117 b7
| | | | | | | +----------------- LC122 b6
| | | | | | | | +--------------- LC124 b5
| | | | | | | | | +------------- LC119 b4
| | | | | | | | | | +----------- LC128 b3
| | | | | | | | | | | +--------- LC127 b2
| | | | | | | | | | | | +------- LC125 b1
| | | | | | | | | | | | | +----- LC121 b0
| | | | | | | | | | | | | | +--- LC118 d5
| | | | | | | | | | | | | | | +- LC126 d7
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC114-> - - * - - - - - - - - - - - * * | - - - - - * - * | <-- b11
LC113-> - - * * - - - - - - - - - - * * | - - - - - * - * | <-- b10
LC115-> - - * * * - - - - - - - - - * * | - - - - - * - * | <-- b9
LC116-> - - * * * * - - - - - - - - - - | - - - - - - * * | <-- b8
LC117-> - - * * * * * - - - - - - - - - | - - - - - - * * | <-- b7
LC122-> - - * * * * * * - - - - - - - - | - - - - - - * * | <-- b6
LC124-> - - * * * * * * * - - - - - - - | - - - - - - - * | <-- b5
LC119-> - - * * * * * * * * - - - - - - | - - - - - - - * | <-- b4
LC128-> - - * * * * * * * * * - - - - - | - - - - - - - * | <-- b3
LC127-> - - * * * * * * * * * * - - - - | - - - - - - - * | <-- b2
LC125-> - - * * * * * * * * * * * - - - | - - - - - - - * | <-- b1
LC121-> - - * * * * * * * * * * * * - - | - - - - - - - * | <-- b0
LC118-> - * - - - - - - - - - - - - * - | - - - - - - - * | <-- d5
LC126-> * - - - - - - - - - - - - - - * | - - - - - - - * | <-- d7
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
10 -> - - * * * * * * * * * * * * - - | - - - - - - - * | <-- cp
12 -> - - - - - - - - - - - - - - * * | - - - - - * * * | <-- en00
11 -> - - - - - - - - - - - - - - * * | - - - - - * * * | <-- en01
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\display\lines.rpt
lines
** EQUATIONS **
clk : INPUT;
cp : INPUT;
en00 : INPUT;
en01 : INPUT;
-- Node name is ':48' = 'b0'
-- Equation name is 'b0', location is LC121, type is buried.
b0 = DFFE( _EQ001 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !b0 & !cp;
-- Node name is ':47' = 'b1'
-- Equation name is 'b1', location is LC125, type is buried.
b1 = DFFE( _EQ002 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !b0 & b1 & !cp
# b0 & !b1 & !cp;
-- Node name is ':46' = 'b2'
-- Equation name is 'b2', location is LC127, type is buried.
b2 = DFFE( _EQ003 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !b1 & b2 & !cp
# !b0 & b2 & !cp
# b0 & b1 & !b2 & !cp;
-- Node name is ':45' = 'b3'
-- Equation name is 'b3', location is LC128, type is buried.
b3 = DFFE( _EQ004 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !b2 & b3 & !cp
# !b1 & b3 & !cp
# !b0 & b3 & !cp
# b0 & b1 & b2 & !b3 & !cp;
-- Node name is ':44' = 'b4'
-- Equation name is 'b4', location is LC119, type is buried.
b4 = DFFE( _EQ005 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !b3 & b4 & !cp
# !b2 & b4 & !cp
# !b1 & b4 & !cp
# !b0 & b4 & !cp
# b0 & b1 & b2 & b3 & !b4 & !cp;
-- Node name is ':43' = 'b5'
-- Equation name is 'b5', location is LC124, type is buried.
b5 = TFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = b0 & b1 & b2 & b3 & b4 & !cp
# b5 & cp;
-- Node name is ':42' = 'b6'
-- Equation name is 'b6', location is LC122, type is buried.
b6 = TFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = b0 & b1 & b2 & b3 & b4 & b5 & !cp
# b6 & cp;
-- Node name is ':41' = 'b7'
-- Equation name is 'b7', location is LC117, type is buried.
b7 = TFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & !cp
# b7 & cp;
-- Node name is ':40' = 'b8'
-- Equation name is 'b8', location is LC116, type is buried.
b8 = TFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & b7 & !cp
# b8 & cp;
-- Node name is ':39' = 'b9'
-- Equation name is 'b9', location is LC115, type is buried.
b9 = TFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & b7 & b8 & !cp
# b9 & cp;
-- Node name is ':38' = 'b10'
-- Equation name is 'b10', location is LC113, type is buried.
b10 = TFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & b7 & b8 & b9 & !cp
# b10 & cp;
-- Node name is ':37' = 'b11'
-- Equation name is 'b11', location is LC114, type is buried.
b11 = TFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & b7 & b8 & b9 & b10 &
!cp
# b11 & cp;
-- Node name is ':52' = 'c0'
-- Equation name is 'c0', location is LC106, type is buried.
c0 = DFFE( _EQ013 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = c0 & en00
# c0 & en01
# !b6 & !b7 & !b8 & !en00 & !en01;
-- Node name is ':53' = 'c1'
-- Equation name is 'c1', location is LC103, type is buried.
c1 = DFFE( _EQ014 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = b6 & !b7 & !b8 & !en00 & !en01
# c1 & en00
# c1 & en01;
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