lineby.rpt

此为用VHDL编写的可实现动感图像的点阵


Device-Specific Information:                             f:\display\lineby.rpt
lineby

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   -    119    H       DFFE   +  t        0      0   0    1    4    8    1  b3 (:13)
   -    116    H       DFFE   +  t        0      0   0    1    3    0    2  b2 (:14)
   -    114    H       DFFE   +  t        0      0   0    1    2    8    3  b1 (:15)
   -    113    H       DFFE   +  t        0      0   0    1    1    8    4  b0 (:16)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                             f:\display\lineby.rpt
lineby

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                                 Logic cells placed in LAB 'H'
        +----------------------- LC120 y0
        | +--------------------- LC128 y1
        | | +------------------- LC126 y2
        | | | +----------------- LC117 y3
        | | | | +--------------- LC115 y4
        | | | | | +------------- LC118 y5
        | | | | | | +----------- LC125 y6
        | | | | | | | +--------- LC123 y7
        | | | | | | | | +------- LC119 b3
        | | | | | | | | | +----- LC116 b2
        | | | | | | | | | | +--- LC114 b1
        | | | | | | | | | | | +- LC113 b0
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC119-> * * * * * * * * * - - - | - - - - - - - * | <-- b3
LC116-> - - - - - - - - * * - - | - - - - - - - * | <-- b2
LC114-> * * * * * * * * * * * - | - - - - - - - * | <-- b1
LC113-> * * * * * * * * * * * * | - - - - - - - * | <-- b0

Pin
83   -> - - - - - - - - - - - - | - - - - - - - - | <-- clk
12   -> - - - - - - - - * * * * | - - - - - - - * | <-- cp


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                             f:\display\lineby.rpt
lineby

** EQUATIONS **

clk      : INPUT;
cp       : INPUT;

-- Node name is ':16' = 'b0' 
-- Equation name is 'b0', location is LC113, type is buried.
b0       = DFFE( _EQ001 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 = !b0 & !cp;

-- Node name is ':15' = 'b1' 
-- Equation name is 'b1', location is LC114, type is buried.
b1       = DFFE( _EQ002 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 =  b0 & !b1 & !cp
         # !b0 &  b1 & !cp;

-- Node name is ':14' = 'b2' 
-- Equation name is 'b2', location is LC116, type is buried.
b2       = DFFE( _EQ003 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 = !b0 &  b2 & !cp
         # !b1 &  b2 & !cp
         #  b0 &  b1 & !b2 & !cp;

-- Node name is ':13' = 'b3' 
-- Equation name is 'b3', location is LC119, type is buried.
b3       = DFFE( _EQ004 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 = !b2 &  b3 & !cp
         # !b0 &  b3 & !cp
         # !b1 &  b3 & !cp
         #  b0 &  b1 &  b2 & !b3 & !cp;

-- Node name is 'y0' = 'c0' 
-- Equation name is 'y0', location is LC120, type is output.
 y0      = DFFE( _EQ005 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 = !b0 & !b1 & !b3;

-- Node name is 'y1' = 'c1' 
-- Equation name is 'y1', location is LC128, type is output.
 y1      = DFFE( _EQ006 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 =  b0 & !b1 & !b3;

-- Node name is 'y2' = 'c2' 
-- Equation name is 'y2', location is LC126, type is output.
 y2      = DFFE( _EQ007 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 = !b0 &  b1 & !b3;

-- Node name is 'y3' = 'c3' 
-- Equation name is 'y3', location is LC117, type is output.
 y3      = DFFE( _EQ008 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 =  b0 &  b1 & !b3;

-- Node name is 'y4' = 'c4' 
-- Equation name is 'y4', location is LC115, type is output.
 y4      = DFFE( _EQ009 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 = !b0 & !b1 &  b3;

-- Node name is 'y5' = 'c5' 
-- Equation name is 'y5', location is LC118, type is output.
 y5      = DFFE( _EQ010 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 =  b0 & !b1 &  b3;

-- Node name is 'y6' = 'c6' 
-- Equation name is 'y6', location is LC125, type is output.
 y6      = DFFE( _EQ011 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ011 = !b0 &  b1 &  b3;

-- Node name is 'y7' = 'c7' 
-- Equation name is 'y7', location is LC123, type is output.
 y7      = DFFE( _EQ012 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ012 =  b0 &  b1 &  b3;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                      f:\display\lineby.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,622K