📄 auto.rpt
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** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC52 b16
| +----------------------------- LC53 b15
| | +--------------------------- LC55 b14
| | | +------------------------- LC51 b13
| | | | +----------------------- LC50 b12
| | | | | +--------------------- LC49 b11
| | | | | | +------------------- LC54 b10
| | | | | | | +----------------- LC56 b9
| | | | | | | | +--------------- LC57 b8
| | | | | | | | | +------------- LC58 b7
| | | | | | | | | | +----------- LC59 b6
| | | | | | | | | | | +--------- LC64 b5
| | | | | | | | | | | | +------- LC63 b4
| | | | | | | | | | | | | +----- LC62 b3
| | | | | | | | | | | | | | +--- LC61 b2
| | | | | | | | | | | | | | | +- LC60 b1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC52 -> * - - - - - - - - - - - - - - - | - - * * | <-- b16
LC53 -> * * - - - - - - - - - - - - - - | - - * * | <-- b15
LC55 -> * * * - - - - - - - - - - - - - | - - - * | <-- b14
LC51 -> * * * * - - - - - - - - - - - - | - * * * | <-- b13
LC50 -> * * * * * - - - - - - - - - - - | - * * * | <-- b12
LC49 -> * * * * * * - - - - - - - - - - | - * * * | <-- b11
LC54 -> * * * * * * * - - - - - - - - - | - - - * | <-- b10
LC56 -> * * * * * * * * - - - - - - - - | - - - * | <-- b9
LC57 -> * * * * * * * * * - - - - - - - | - - - * | <-- b8
LC58 -> * * * * * * * * * * - - - - - - | - - - * | <-- b7
LC59 -> * * * * * * * * * * * - - - - - | - - - * | <-- b6
LC64 -> * * * * * * * * * * * * - - - - | - - - * | <-- b5
LC63 -> * * * * * * * * * * * * * - - - | - - - * | <-- b4
LC62 -> * * * * * * * * * * * * * * - - | - - - * | <-- b3
LC61 -> * * * * * * * * * * * * * * * - | - - - * | <-- b2
LC60 -> * * * * * * * * * * * * * * * * | - - - * | <-- b1
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
12 -> * * * * * * * * * * * * * * * * | - - * * | <-- cp
LC34 -> * * * * * * * * * * * * * * * * | - - * * | <-- b0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\display\auto.rpt
auto
** EQUATIONS **
clk : INPUT;
cp : INPUT;
-- Node name is ':40' = 'b0'
-- Equation name is 'b0', location is LC034, type is buried.
b0 = DFFE( _EQ001 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !b0 & !cp;
-- Node name is ':39' = 'b1'
-- Equation name is 'b1', location is LC060, type is buried.
b1 = DFFE( _EQ002 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !b0 & b1 & !cp
# b0 & !b1 & !cp;
-- Node name is ':38' = 'b2'
-- Equation name is 'b2', location is LC061, type is buried.
b2 = DFFE( _EQ003 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !b1 & b2 & !cp
# !b0 & b2 & !cp
# b0 & b1 & !b2 & !cp;
-- Node name is ':37' = 'b3'
-- Equation name is 'b3', location is LC062, type is buried.
b3 = DFFE( _EQ004 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !b2 & b3 & !cp
# !b1 & b3 & !cp
# !b0 & b3 & !cp
# b0 & b1 & b2 & !b3 & !cp;
-- Node name is ':36' = 'b4'
-- Equation name is 'b4', location is LC063, type is buried.
b4 = DFFE( _EQ005 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !b3 & b4 & !cp
# !b2 & b4 & !cp
# !b1 & b4 & !cp
# !b0 & b4 & !cp
# b0 & b1 & b2 & b3 & !b4 & !cp;
-- Node name is ':35' = 'b5'
-- Equation name is 'b5', location is LC064, type is buried.
b5 = TFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = b0 & b1 & b2 & b3 & b4 & !cp
# b5 & cp;
-- Node name is ':34' = 'b6'
-- Equation name is 'b6', location is LC059, type is buried.
b6 = TFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = b0 & b1 & b2 & b3 & b4 & b5 & !cp
# b6 & cp;
-- Node name is ':33' = 'b7'
-- Equation name is 'b7', location is LC058, type is buried.
b7 = TFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & !cp
# b7 & cp;
-- Node name is ':32' = 'b8'
-- Equation name is 'b8', location is LC057, type is buried.
b8 = TFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & b7 & !cp
# b8 & cp;
-- Node name is ':31' = 'b9'
-- Equation name is 'b9', location is LC056, type is buried.
b9 = TFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & b7 & b8 & !cp
# b9 & cp;
-- Node name is ':30' = 'b10'
-- Equation name is 'b10', location is LC054, type is buried.
b10 = TFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & b7 & b8 & b9 & !cp
# b10 & cp;
-- Node name is ':29' = 'b11'
-- Equation name is 'b11', location is LC049, type is buried.
b11 = TFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & b7 & b8 & b9 & b10 &
!cp
# b11 & cp;
-- Node name is ':28' = 'b12'
-- Equation name is 'b12', location is LC050, type is buried.
b12 = TFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & b7 & b8 & b9 & b10 &
b11 & !cp
# b12 & cp;
-- Node name is ':27' = 'b13'
-- Equation name is 'b13', location is LC051, type is buried.
b13 = TFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & b7 & b8 & b9 & b10 &
b11 & b12 & !cp
# b13 & cp;
-- Node name is ':26' = 'b14'
-- Equation name is 'b14', location is LC055, type is buried.
b14 = TFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & b7 & b8 & b9 & b10 &
b11 & b12 & b13 & !cp
# b14 & cp;
-- Node name is ':25' = 'b15'
-- Equation name is 'b15', location is LC053, type is buried.
b15 = TFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & b7 & b8 & b9 & b10 &
b11 & b12 & b13 & b14 & !cp
# b15 & cp;
-- Node name is ':24' = 'b16'
-- Equation name is 'b16', location is LC052, type is buried.
b16 = TFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & b7 & b8 & b9 & b10 &
b11 & b12 & b13 & b14 & b15 & !cp
# b16 & cp;
-- Node name is 't0' = 'd0'
-- Equation name is 't0', location is LC030, type is output.
t0 = DFFE( VCC $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 't1' = 'd1'
-- Equation name is 't1', location is LC040, type is output.
t1 = DFFE( _EQ018 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ018 = !b11 & !b12 & !b13
# !b15
# b16;
-- Node name is 't2' = 'd2'
-- Equation name is 't2', location is LC033, type is output.
t2 = DFFE( _EQ019 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ019 = b12 & !b13 & b15 & !b16
# !b11 & b12 & b15 & !b16
# b11 & !b12 & b13 & b15 & !b16
# !b11 & !b12 & !b13;
-- Node name is 't3' = 'd3'
-- Equation name is 't3', location is LC046, type is output.
t3 = DFFE( _EQ020 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ020 = !b11 & !b13
# !b11 & b12
# b12 & !b13
# b11 & !b12 & b13;
-- Node name is 't4' = 'd4'
-- Equation name is 't4', location is LC041, type is output.
t4 = DFFE( _EQ021 $ b12, GLOBAL( clk), VCC, VCC, VCC);
_EQ021 = !b11 & !b12 & !b13
# b15 & !b16 & _X001
# b11 & b13 & _X002;
_X001 = EXP( b11 & b13);
_X002 = EXP( b15 & !b16);
-- Node name is 't5' = 'd5'
-- Equation name is 't5', location is LC037, type is output.
t5 = DFFE( _EQ022 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ022 = !b12 & !b13
# !b11 & !b12
# b15 & !b16
# b11 & b12 & b13;
-- Node name is 't6' = 'd6'
-- Equation name is 't6', location is LC004, type is output.
t6 = DFFE( VCC $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 't7' = 'd7'
-- Equation name is 't7', location is LC003, type is output.
t7 = DFFE( VCC $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'y0' = 'c0'
-- Equation name is 'y0', location is LC035, type is output.
y0 = DFFE( _EQ023 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ023 = !b11 & !b12 & !b13;
-- Node name is 'y1' = 'c1'
-- Equation name is 'y1', location is LC036, type is output.
y1 = DFFE( _EQ024 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ024 = b11 & !b12 & !b13;
-- Node name is 'y2' = 'c2'
-- Equation name is 'y2', location is LC017, type is output.
y2 = DFFE( _EQ025 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ025 = !b11 & b12 & !b13;
-- Node name is 'y3' = 'c3'
-- Equation name is 'y3', location is LC019, type is output.
y3 = DFFE( _EQ026 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ026 = b11 & b12 & !b13;
-- Node name is 'y4' = 'c4'
-- Equation name is 'y4', location is LC020, type is output.
y4 = DFFE( _EQ027 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ027 = !b11 & !b12 & b13;
-- Node name is 'y5' = 'c5'
-- Equation name is 'y5', location is LC025, type is output.
y5 = DFFE( _EQ028 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ028 = b11 & !b12 & b13;
-- Node name is 'y6' = 'c6'
-- Equation name is 'y6', location is LC024, type is output.
y6 = DFFE( _EQ029 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ029 = !b11 & b12 & b13;
-- Node name is 'y7' = 'c7'
-- Equation name is 'y7', location is LC021, type is output.
y7 = DFFE( _EQ030 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ030 = b11 & b12 & b13;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information f:\display\auto.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 6,172K
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