manualswitch.rpt

此为用VHDL编写的可实现动感图像的点阵

manualswitch

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  73    115    H         FF      t        0      0   0    0    1    1    0  en0 (:10)
  74    117    H         FF      t        0      0   0    0    2    0    0  en1 (:9)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                       f:\display\manualswitch.rpt
manualswitch

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (75)   118    H       DFFE   +  t        0      0   0    1    3    0    4  jsp2 (:5)
   -    113    H       DFFE   +  t        0      0   0    1    3    0    3  jsp1 (:6)
   -    114    H       DFFE   +  t        0      0   0    1    3    0    3  jsp0 (:7)
   -    116    H       DFFE   +  t        0      0   0    1    1    2    0  cp (:8)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                       f:\display\manualswitch.rpt
manualswitch

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                     Logic cells placed in LAB 'H'
        +----------- LC115 en0
        | +--------- LC117 en1
        | | +------- LC118 jsp2
        | | | +----- LC113 jsp1
        | | | | +--- LC114 jsp0
        | | | | | +- LC116 cp
        | | | | | | 
        | | | | | |   Other LABs fed by signals
        | | | | | |   that feed LAB 'H'
LC      | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC115-> * * - - - - | - - - - - - - * | <-- en0
LC118-> - - * * * * | - - - - - - - * | <-- jsp2
LC113-> - - * * * - | - - - - - - - * | <-- jsp1
LC114-> - - * * * - | - - - - - - - * | <-- jsp0
LC116-> * * - - - - | - - - - - - - * | <-- cp

Pin
83   -> - - - - - - | - - - - - - - - | <-- clk
12   -> - - * * * * | - - - - - - - * | <-- key


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                       f:\display\manualswitch.rpt
manualswitch

** EQUATIONS **

clk      : INPUT;
key      : INPUT;

-- Node name is ':8' = 'cp' 
-- Equation name is 'cp', location is LC116, type is buried.
cp       = DFFE( _EQ001 $  VCC, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 = !jsp2
         #  key;

-- Node name is 'en0' = 'count0' 
-- Equation name is 'en0', location is LC115, type is output.
 en0     = TFFE( VCC,  cp,  VCC,  VCC,  VCC);

-- Node name is 'en1' = 'count1' 
-- Equation name is 'en1', location is LC117, type is output.
 en1     = TFFE( en0,  cp,  VCC,  VCC,  VCC);

-- Node name is ':7' = 'jsp0' 
-- Equation name is 'jsp0', location is LC114, type is buried.
jsp0     = DFFE( _EQ002 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 = !jsp0 &  key
         # !jsp1 &  jsp2 &  key
         #  jsp0 & !jsp2 & !key;

-- Node name is ':6' = 'jsp1' 
-- Equation name is 'jsp1', location is LC113, type is buried.
jsp1     = DFFE( _EQ003 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 = !jsp0 &  jsp1 &  key
         #  jsp0 & !jsp1 & !jsp2 &  key
         #  jsp1 & !jsp2 & !key;

-- Node name is ':5' = 'jsp2' 
-- Equation name is 'jsp2', location is LC118, type is buried.
jsp2     = DFFE( _EQ004 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 = !jsp1 &  jsp2 &  key
         # !jsp0 &  jsp2 &  key
         #  jsp0 &  jsp1 & !jsp2 &  key;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                f:\display\manualswitch.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,607K