📄 os_cpu_a.s
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;********************************************************************************************************
; uC/OS-II
; The Real-Time Kernel
;
; (c) Copyright 1992-2002, Jean J. Labrosse, Weston, FL
; All Rights Reserved
;
; ARM7 Port
; IAR C Compiler
;
; File : OS_CPU_A.ASM
; By : Jean J. Labrosse
; Michael Anburaj Email : michaelanburaj@hotmail.com
; Web : http://geocities.com/michaelanburaj/
;********************************************************************************************************
EXTERN OSRunning ; External references
EXTERN OSTCBCur
EXTERN OSTCBHighRdy
EXTERN OSPrioCur
EXTERN OSPrioHighRdy
EXTERN OSIntCtxSwFlag
EXTERN OSIntEnter
EXTERN OSIntExit
EXTERN OSTaskSwHook
EXTERN OS_CPU_IRQ_Handler
PUBLIC OSStartHighRdy ; Functions declared in this file
PUBLIC OSCtxSw
PUBLIC OS_CPU_SaveSR
PUBLIC OS_CPU_RestoreSR
PUBLIC OS_CPU_IRQ_ISR
NO_INT EQU 0xC0 ; Mask used to disable interrupts (Both FIR and IRQ)
;*********************************************************************************************************
; INTERRUPT VECTORS
;*********************************************************************************************************
COMMON INTVEC:CODE:ROOT(2)
CODE32
ORG 0x18
B OS_CPU_IRQ_ISR
ORG 0x1C
B OS_CPU_FIQ_ISR
;*********************************************************************************************************
; START MULTITASKING
; void OSStartHighRdy(void)
;
; Note : OSStartHighRdy() MUST:
; a) Call OSTaskSwHook() then,
; b) Set OSRunning to TRUE,
; c) Switch to the highest priority task.
;*********************************************************************************************************
RSEG NEARFUNC_A:CODE:NOROOT(2)
CODE32
OSStartHighRdy
BL OSTaskSwHook ; Call user defined task switch hook
LDR R4,??OS_Running ; OSRunning = TRUE
MOV R5,#1
STRB R5,[R4]
LDR R4,??OS_TCBHighRdy ; Get highest priority task TCB address
LDR R4,[R4] ; get stack pointer
LDR SP,[R4] ; switch to the new stack
LDMFD SP!,{R4} ; pop new task's spsr
MSR SPSR_cxsf,R4
LDMFD SP!,{R4} ; pop new task's CPSR
MSR CPSR_cxsf,R4
LDMFD SP!,{R0-R12,LR,PC} ; pop new task's r0-r12,lr & pc
;*********************************************************************************************************
; PERFORM A CONTEXT SWITCH (From task level)
;
; Note(s): Upon entry:
; OSTCBCur points to the OS_TCB of the task to suspend
; OSTCBHighRdy points to the OS_TCB of the task to resume
;*********************************************************************************************************
RSEG NEARFUNC_A:CODE:NOROOT(2)
CODE32
OSCtxSw
STMFD SP!,{LR} ; push pc (lr should be pushed in place of PC)
STMFD SP!,{R0-R12,LR} ; push lr & register file
MRS R4,CPSR
STMFD SP!,{R4} ; push current psr
MRS R4,SPSR
STMFD SP!,{R4} ; push current spsr
LDR R4,??OS_PrioCur ; OSPrioCur = OSPrioHighRdy
LDR R5,??OS_PrioHighRdy
LDRB R6,[r5]
STRB R6,[r4]
LDR R4,??OS_TCBCur ; Get current task's OS_TCB address
LDR R5,[r4]
STR SP,[r5] ; store sp in preempted tasks's TCB
BL OSTaskSwHook ; call Task Switch Hook
LDR R6,??OS_TCBHighRdy ; Get highest priority task's OS_TCB address
LDR R6,[R6]
LDR SP,[R6] ; get new task's stack pointer
STR R6,[R4] ; OSTCBCur = OSTCBHighRdy
LDMFD SP!,{R4} ; pop new task's spsr
MSR SPSR_cxsf,R4
LDMFD SP!,{R4} ; pop new task's psr
MSR CPSR_cxsf,r4
LDMFD SP!,{R0-R12,LR,PC} ; pop new task's r0-r12,lr & pc
;*********************************************************************************************************
; CRITICAL SECTION METHOD 3 FUNCTIONS
;
; Description: Disable/Enable interrupts by preserving the state of interrupts. Generally speaking you
; would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then
; disable interrupts. 'cpu_sr' is allocated in all of uC/OS-II's functions that need to
; disable interrupts. You would restore the interrupt disable state by copying back 'cpu_sr'
; into the CPU's status register.
;
; Prototypes : OS_CPU_SR OS_CPU_SaveSR(void);
; void OS_CPU_RestoreSR(OS_CPU_SR cpu_sr);
;
;
; Note(s) : 1) These functions are used in general like this:
;
; void Task (void *data)
; {
; #if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */
; OS_CPU_SR cpu_sr;
; #endif
;
; :
; :
; OS_ENTER_CRITICAL(); /* cpu_sr = OS_CPU_SaveSR(); */
; :
; :
; OS_EXIT_CRITICAL(); /* OS_CPU_RestoreSR(cpu_sr); */
; :
; :
; }
;
; 2) OS_CPU_SaveSR() is implemented as recommended by Atmel's application note:
;
; "Disabling Interrupts at Processor Level"
;*********************************************************************************************************
OS_CPU_SaveSR
MRS R0,CPSR ; Set IRQ and FIQ bits in CPSR to disable all interrupts
ORR R1,R0,#NO_INT
MSR CPSR_c,R1
MRS R1,CPSR ; Confirm that CPSR contains the proper interrupt disable flags
AND R1,R1,#NO_INT
CMP R1,#NO_INT
BNE OS_CPU_SaveSR ; Not properly disabled (try again)
MOV PC,LR ; Disabled, return the original CPSR contents in R0
OS_CPU_RestoreSR
MSR CPSR_c,R0
MOV PC,LR
;*********************************************************************************************************
; IRQ HANDLER
;
; Description: This handles all the IRQs
;*********************************************************************************************************
OS_CPU_IRQ_ISR
STMFD SP!,{R0-R3,R12,LR}
BL OSIntEnter ; Indicate beginning of ISR
BL OS_CPU_IRQ_Handler ; Handle interrupt
BL OSIntExit ; Indicate end of ISR
LDR R0,??OS_IntCtxSwFlag ; See if we need to do a context switch
LDR R1,[R0]
CMP R1,#1
BEQ OS_IntCtxSw ; Yes, Switch to Higher Priority Task
LDMFD SP!,{R0-R3,R12,LR} ; No, Restore registers of interrupted task's stack
SUBS PC,LR,#4 ; Return from IRQ
;*********************************************************************************************************
; FIQ HANDLER
;
; Description: This handles all the FIQs
;*********************************************************************************************************
OS_CPU_FIQ_ISR
STMFD SP!,{R0-R3,R12,LR}
BL OSIntEnter ; Indicate beginning of ISR
BL OS_CPU_IRQ_Handler ; Handle interrupt
BL OSIntExit ; Indicate end of ISR
LDR R0,??OS_IntCtxSwFlag ; See if we need to do a context switch
LDR R1,[R0]
CMP R1,#1
BEQ OS_IntCtxSw ; Yes, Switch to Higher Priority Task
LDMFD SP!,{R0-R3,R12,LR} ; No, Restore registers of interrupted task's stack
SUBS PC,LR,#4 ; Return from IRQ
;*********************************************************************************************************
; INTERRUPT LEVEL CONTEXT SWITCH
;
; Description: This code performs a context switch if a higher priority task has been made ready-to-run
; during an ISR.
;*********************************************************************************************************
OS_IntCtxSw
LDR R0,??OS_IntCtxSwFlag ; OSIntCtxSwFlag = FALSE
MOV R1,#0
STR R1,[R0]
LDMFD SP!,{R0-R3,R12,LR} ; Clean up IRQ stack
STMFD SP!,{R0-R3} ; We will use R0-R3 as temporary registers
MOV R1,SP
ADD SP,SP,#16
SUB R2,LR,#4
MRS R3,SPSR ; Disable interrupts for when we go back to SVC mode
ORR R0,R3,#NO_INT
MSR SPSR_c,R0
LDR R0,=.+8 ; Switch back to SVC mode (Code below, current location + 2 instructions)
MOVS PC,R0 ; Restore PC and CPSR
; SAVE OLD TASK'S CONTEXT ONTO OLD TASK'S STACK
STMFD SP!,{R2} ; Push task's PC
STMFD SP!,{R4-R12,LR} ; Push task's LR,R12-R4
MOV R4,R1 ; Move R0-R3 from IRQ stack to SVC stack
MOV R5,R3
LDMFD R4!,{R0-R3} ; Load R0-R3 from IRQ stack
STMFD SP!,{R0-R3} ; Push R0-R3
STMFD SP!,{R5} ; Push task's CPSR
MRS R4,SPSR
STMFD SP!,{R4} ; Push task's SPSR
LDR R4,??OS_PrioCur ; OSPrioCur = OSPrioHighRdy
LDR R5,??OS_PrioHighRdy
LDRB R5,[R5]
STRB R5,[R4]
LDR R4,??OS_TCBCur ; Get current task's OS_TCB address
LDR R5,[R4]
STR SP,[R5] ; store sp in preempted tasks's TCB
BL OSTaskSwHook ; call Task Switch Hook
LDR R6,??OS_TCBHighRdy ; Get highest priority task's OS_TCB address
LDR R6,[R6]
LDR SP,[R6] ; get new task's stack pointer
STR R6,[R4] ; OSTCBCur = OSTCBHighRdy
LDMFD SP!,{R4} ; pop new task's spsr
MSR SPSR_cxsf,R4
LDMFD SP!,{R4} ; pop new task's psr
MSR CPSR_cxsf,R4
LDMFD SP!,{R0-R12,LR,PC} ; pop new task's r0-r12,lr & pc
;*********************************************************************************************************
; POINTERS TO VARIABLES
;*********************************************************************************************************
DATA
??OS_IntCtxSwFlag:
DC32 OSIntCtxSwFlag
??OS_PrioCur:
DC32 OSPrioCur
??OS_PrioHighRdy:
DC32 OSPrioHighRdy
??OS_Running:
DC32 OSRunning
??OS_TCBCur:
DC32 OSTCBCur
??OS_TCBHighRdy:
DC32 OSTCBHighRdy
END
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