📄 i2cbus.lst
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* M16C FAMILY ASSEMBLER * SOURCE LIST Mon Sep 10 15:02:41 2001 PAGE 011
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
615 0039D 7E8F791F bclr 1,PD7 ; Set SCL pin direction to input.
616 003A1 sl_s_l1: ;
617 003A1 7EBF691F btst 1,P7 ; ----- Wait for SCL to go high.
618 003A5 6AFB jz sl_s_l1 ; --/
619 003A7 C70A7803 S mov.b #0ah,U2MR ; Set use external clock.
620 003AB 731F7A03 mov.w R1,U2TB ; Copy data in R1 to UART2 transmit buffer.
621 003AF 7E9FB21B bset 2,U2SMR2 ; Set 9th bit low, hold function enable, keep low at 9th bit
622 003B3 7E8F781F bclr 0,PD7 ; Set SDA pin direction to input.
623 ;
624 003B7 7EBF0000r btst 1,m_iic ; Test for arbitration lost.
625 003BB 6A04 jz sl_snd10 ; if arbitration has not been lost, jump to s1_and10
626 003BD F5C900 W jsr abt_lost ; Else arbitration has been lost, jump to abt_lost.
627 003C0 sl_snd10: ;
628 003C0 C7040000r S mov.b #04h,m_iic ; Set I2C mode condition to set slave transmit mode.
629 003C4 F4BC00 W jmp u2rcv_int_end ;
630 ;;; ===========================================================================
631 ;; Receive ACK to 1st data byte and start second data byte.
632 ;;; ===========================================================================
633 003C7 04 .align ;
634 003C8 sl_rcv_n: ;
635 .if DEBUG == 1 ; --- DEBUG ---
636 003C8 7E9F8C1F bset 4,dp ; --- DEBUG ---
637 .endif ; --- DEBUG ---
638 003CC 7EBFB21B btst 2,U2SMR2 ; Bit test 9bit low.
639 003D0 6E04 * jz u2rcv_int_end ; if 0 jump.
F4AE00
640 ;
641 003D5 72F20000r mov.b sd_p,R1L ; Load slave receive data counter to R1L.
642 003D9 D803 Q mov.b #00h,R1H ; Set R1H to zero.
643 003DB 73F40000r mov.w slave_ram,A0 ; Set A0 to slave ram address.
644 003DF A114 add.w R1,A0 ; Add slave receive data counter to slave ram address.
645 ;
646 003E1 73F17E03 mov.w U2RB,R1 ; Copy data receive in UART2 receive buffer to R1.
647 003E5 7EB108 btst 8,R1 ; Test 8th bit
648 003E8 76A2 rolc.b R1L ; If 8th bit high restore data to R1L.
649 ;;;
650 ;;;
651 ;;;
652 003EA 7EBF0000r btst 7,sd_p ; Test bit 7 of slave receive data counter.
653 003EE 6A06 jz sl_rcv_n03 ; If bit 7 is 0 them jump to s1_rcv_n03.
654 003F0 722F0000r mov.b R1L,sd_p ; Copy R1L to slave data counter.
655 003F4 64 S jmp sl_rcv_n05 ;
656 003F5 sl_rcv_n03: ;
657 003F5 7226 mov.b R1L,[A0] ; copy RIL to slave data ram location pointer to by A0.
658 003F7 A70000r inc.b sd_p ; Increment slave data counter.
659 003FA sl_rcv_n05: ;
660 003FA 977F0000r S and.b #07fh,sd_p ; Set 8th bit of slave data pointer to 0.
661 ;;;
662 ;;;
663 ;;;
664 003FE 7E8FB21B bclr 2,U2SMR2 ; After 9th bit disable keep low function.
665 00402 sl_r_ln: ;
666 00402 7EBF691F btst 1,P7 ; ----- Wait for SCL to go high.
667 00406 6AFB jz sl_r_ln ; ---/
668 00408 C70A7803 S mov.b #0ah,U2MR ; Set, use external clock.
669 0040C 75CF7A03FF00 mov.w #00ffh,U2TB ; Place dummy data into UART2 transmit buffer.
670 00412 7E9FB21B bset 2,U2SMR2 ; Enable keep low function.
671 00416 FE6A B jmp u2rcv_int_end ;
672 ;;; ===========================================================================
673 ;; Slave transmit data
674 ;; Test for ACK and send next data byte.
675 ;;; ===========================================================================
* M16C FAMILY ASSEMBLER * SOURCE LIST Mon Sep 10 15:02:41 2001 PAGE 012
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
676 .align ;
677 00418 sl_snd_n: ;
678 .if DEBUG == 1 ; --- DEBUG ---
679 00418 7E9F8B1F bset 3,dp ; --- DEBUG ---
680 .endif ; --- DEBUG ---
681 0041C 72F20000r mov.b sd_p,R1L ; Copy slave data counter to R1L.
682 00420 D803 Q mov.b #00h,R1H ; Init R1H to zero.
683 00422 73F40000r mov.w slave_ram,A0 ; Copy slave ram address to A0.
684 00426 A114 add.w R1,A0 ; Add slave data counter to slave ram address.
685 00428 7262 mov.b [A0],R1L ; Copy data pointed to by A0 to R1L
686 0042A D813 Q mov.b #01h,R1H ; Init bit 9 of R1 to nack.
687 0042C 7E8FB21B bclr 2,U2SMR2 ; After 9th bit disable keep low function.
688 00430 sl_s_ln: ;
689 00430 7EBF691F btst 1,P7 ; ---- Wait for SCL to go high.
690 00434 6AFB jz sl_s_ln ; --/
691 00436 7EBF681F btst 0,P7 ; Test logic value of SDA.
692 0043A 6E17 jnz sl_s_end ; If no ACK, jump to al_s_end.
693 ;; ACK received.
694 0043C C70A7803 S mov.b #0ah,U2MR ; Set SCL to external clock.
695 00440 731F7A03 mov.w R1,U2TB ; Copy data from R1 to UART2 transmit buffer.
696 00444 7E9FB21B bset 2,U2SMR2 ; Enable keep low function.
697 00448 A70000r inc.b sd_p ; Increment slave data counter.
698 0044B 977F0000r S and.b #07fh,sd_p ; Set bit 8th of slave data counter to zero.
699 0044F FE31 B jmp u2rcv_int_end ;
700 ;;; ----------------------------
701 00451 04 .align ;
702 00452 sl_s_end: ;
703 00452 C70A7803 S mov.b #0ah,U2MR ;
704 00456 C7D17603 S mov.b #0d1h,U2SMR2 ;
705 0045A B70000r Z mov.b #00h,m_iic ; Set I2C bus condition register to wait mode stop to start
706 0045D FE23 B jmp u2rcv_int_end ;
707 ;;; ----------------------------
708 0045F 04 .align ;
709 00460 slave_taiki: ; Slave wait mode stop.
710 00460 97085000 S and.b #08h,S2RIC ;
711 00464 7E9FB61B bset 6,U2SMR2 ; Set SDA pin to input.
712 00468 7E8FB21B bclr 2,U2SMR2 ; Disable 9th bit keep low function.
713 0046C sl_t_l1: ;
714 0046C 7EBF691F btst 1,P7 ; ----- Wait for SCL input to go high.
715 00470 6AFB jz sl_t_l1 ; --/
716 00472 7E9F681F bset 0,P7 ; Set SDA to high "high impedance".
717 00476 C7D17603 S mov.b #0d1h,U2SMR2 ; ---- Set up UART for next I2C bus communication.
718 0047A C70A7803 S mov.b #0ah,U2MR ; --/
719 0047E B70000r Z mov.b #00h,m_iic ; Set I2C bus condition register to wait mode stop to start
720 00481 u2rcv_int_end: ;
721 00481 ED12 popm A0,R1 ; Pop registers from stack.
722 .if DEBUG == 1 ; --- DEBUG ---
723 00483 B7F103 Z mov.b #00h,dp ; --- DEBUG ---
724 .endif ; --- DEBUG ---
725 00486 FB reit ;
726 ;;; --------------------------------------------------------------------------
727 ;; Test for Arbitration lost function.
728 ;;; --------------------------------------------------------------------------
729 ;;
730 00487 abt_lost: ;
731 .if DEBUG == 1 ; --- DEBUG ---
732 00487 7E9F8F1F bset 7,dp ; --- DEBUG ---
733 .endif ; --- DEBUG ---
734 0048B D832 Q mov.b #03h,R1L ; Return error #3
735 0048D 744F0000r push.b md_cnt ; Push master data count onto stack.
736 00491 7EBF0000r btst 0,m_iic ; Test I2C bus condition register for Read or Write.
737 00495 6806 jc abt_lost10 ; If Read jump.
* M16C FAMILY ASSEMBLER * SOURCE LIST Mon Sep 10 15:02:41 2001 PAGE 013
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
738 ;; ; Else Write.
739 00497 FD000000r A jsr $iic_mw_end ; Jump to sub-routine.
740 0049B 63 S jmp abt_lost_end ; Jump to abt_lost_end.
741 .align ;
742 0049C abt_lost10: ;
743 0049C FD000000r A jsr $iic_mr_end ; Jump to sub-routine.
744 004A0 abt_lost_end: ;
745 004A0 74DF0000r pop.b md_cnt ; Pop master data count from stack.
746 004A4 B70000r Z mov.b #00h,md_cnt ; Init master data count to 0.
747 004A7 F3 rts ;
748 ;;; --------------------------------------------------------------------------
749 ;; Make stop condition.
750 ;;; --------------------------------------------------------------------------
751 ;;
752 ;;
753 004A8 make_stop:
754 004A8 97FCED03 S and.b #0fch,P7 ; Set SDA and SCL to low output.
755 004AC 9F03EF03 S or.b #03h,PD7 ;
756 004B0 F55100 W jsr wait_0us ; Wait 0us
757 004B3 B77803 Z mov.b #00h,U2MR ; Disable I2C mode
758 004B6 7E8F691F bclr 1,P7 ; SCL = L
759 004BA 7E8F681F bclr 0,P7 ; SDA = L
760 004BE F53100 W jsr wait_5usec ; New counter delay routine by Bruce Embry, July 1999.
761 004C1 7E8F791F bclr 1,PD7 ; Set SCLD to high impedance.
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