📄 i2cbus.lst
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458 0026F 7E8FB51B bclr 5,U2SMR2 ; Clear bit SWC2, "SCL goes high and enable transmission of
459 00273 F40D02 W jmp u2rcv_int_end ;
460 ;;; ---------------------------------------------------------------------------
461 ;; END of Master transmission.
462 ;;; ---------------------------------------------------------------------------
463 .align ;
464 00276 snd_nack_err_1: ;
465 00276 D812 Q mov.b #01h,R1L ; Return value; "NO ACK" ---> ID error.
466 00278 66 S jmp ms_s_end ;
467 ;;; ----------------------------
468 00279 04 .align ;
469 0027A snd_nack_err_n: ;
470 0027A D822 Q mov.b #02h,R1L ; Return value "NO ACK" ---> data error.
471 0027C 62 S jmp ms_s_end ;
472 ;;; ----------------------------
473 0027D 04 .align ;
474 0027E snd_end: ; Normal end!
475 0027E D802 Q mov.b #00h,R1L ; Clear R1L.
476 00280 ms_s_end: ;
477 00280 F52702 W jsr make_stop ; Jump sub-routine make stop function.
478 00283 B70000r Z mov.b #00h,m_iic ; Set I2C bus mode condition to Stop to Start condition.
479 ;;; for C
480 00286 744F0000r push.b md_cnt ; Push master data counter on to stack.
481 0028A FD000000r A jsr $iic_mw_end ; Jump sub-routine iic_mw_end, "part of c code retu
482 0028E 74DF0000r pop.b md_cnt ; Pop master data counter from stack.
483 00292 B70000r Z mov.b #00h,md_cnt ; Init master data counter for next I2C bus operation.
484 00295 F4EB01 W jmp u2rcv_int_end ; End interrupt service routine.
485 ;;; ===========================================================================
486 ;; Master receive "READ"
487 ;;; ===========================================================================
488 .align ;
489 00298 ms_rcv_1: ;
490 .if DEBUG == 1 ; ---DEBUG---
* M16C FAMILY ASSEMBLER * SOURCE LIST Mon Sep 10 15:02:41 2001 PAGE 009
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
491 00298 7E9F8A1F bset 2,dp ; ---DEBUG---
492 .endif ; ---DEBUG---
493 0029C C7837603 S mov.b #83h,U2SMR2 ; SCL output disable.
494 002A0 ms_r_l1: ;
495 002A0 7EBF691F btst 1,P7 ; --- Wait for SCL to go high.
496 002A4 6AFB jz ms_r_l1 ; -/
497 002A6 7EBF681F btst 0,P7 ; Bit test SDA for ACK.
498 002AA 6E7B jnz rcv_nack_err ; If no ACK received jump to rcv_nack_err.
499 ;
500
501 ;; ELSE
502 ;;1999,6,25 miho ; Code added to fixed problem with number of data bytes bein
503 002AC E7000000r S cmp.b #0,mr_lng ; Compare master read data length.
504 002B0 6A08 jz point0 ; If zero jump to point0.
505 002B2 75CF7A03FF00 mov.w #0ffh,U2TB ; else init UART2 transmit buffer to 0FF, "ACK."
506 002B8 65 S jmp point1 ;
507 002B9 point0:
508 002B9 75CF7A03FF01 mov.w #1ffh,U2TB ; Bit8 =1 "NO ACK."
509 002BF point1:
510 ;;;
511 002BF 7E9FB21B bset 2,U2SMR2 ; At end of address comparison, "see note 3.4.1."
512 002C3 F52002 W jsr wait_2usec ; New counter delay July 1999 by Bruce Embry.
513 002C6 7E9FB51B bset 5,U2SMR2 ; First bit startup, disable SCL .
514 002CA F53002 W jsr wait_20usec ; New counter delay by Bruce Embry, July 1999.
515 002CD 7E8FB51B bclr 5,U2SMR2 ; Bit clear SWC2, enable SCL clk and start reception of next
516 002D1 F4AF01 W jmp u2rcv_int_end ; Jump to end of interrupt service routine.
517 ;;; ===========================================================================
518 ;; Master receive "DATA"
519 ;;; ===========================================================================
520 .align ;
521 002D4 ms_rcv_n: ;
522 .if DEBUG == 1 ; ---DEBUG---
523 002D4 7E9F8A1F bset 2,dp ; ---DEBUG---
524 .endif ; ---DEBUG---
525 ;
526 002D8 D803 Q mov.b #00h,R1H ; Init R1H
527 002DA 72F20000r mov.b md_cnt,R1L ; Load master receive data count.
528 002DE 73F40000r mov.w mr_data,A0 ; Copy master receive data pointer to A0
529 002E2 A114 add.w R1,A0 ; Calculate data pointer offset.
530 ;
531 002E4 73F17E03 mov.w U2RB,R1 ; Copy UART2 receive buffer to R1
532 002E8 7EB108 btst 8,R1 ; Test 8th bit
533 002EB 76A2 rolc.b R1L ; if 8th bit == 1, then shift left Restoring normal
534 002ED 7226 mov.b R1L,[A0] ; Copy data to memory location pointed to by A0.
535 002EF A70000r inc.b md_cnt ; Increment master data receive counter.
536 002F2 C0FF0000r0000r cmp.b mr_lng,md_cnt ; Compare data receive count to expected data receive count.
537 002F8 76A3 rolc.b R1H ; ack/nack Rotate right bit 9.
538 002FA D8F2 Q mov.b #0ffh,R1L ;
539 002FC 7E8FB21B bclr 2,U2SMR2 ; First bit hold on, "every byte."
540 00300 ms_r_ln: ;
541 00300 7EBF691F btst 1,P7 ; ---- Wait for SCL to go high.
542 00304 6AFB jz ms_r_ln ; --/
543 00306 7EBF681F btst 0,P7 ; Bit test SDA for ACK.
544 0030A 6E1F jnz rcv_end ; If NO ACK then jump to rcv_end.
545 0030C 731F7A03 mov.w R1,U2TB ; Else ACK received, copy R1 data to UART2 transmit buffer.
546 00310 7E9FB21B bset 2,U2SMR2 ; Set SWC enable, SCL clock on hold enabled.
547 00314 F5CF01 W jsr wait_2usec ; New counter delay by Bruce Embry, July 1999.
548 00317 7E9FB51B bset 5,U2SMR2 ; Hold SCL low.
549 0031B F5DA01 W jsr wait_15usec ; New counter delay by Bruce Embry, July 1999.
550 0031E 7E8FB51B bclr 5,U2SMR2 ; Release SCL and start Master data receive.
551 00322 F45E01 W jmp u2rcv_int_end ;
552 ;;; -----------------------------------------------------------------------------
* M16C FAMILY ASSEMBLER * SOURCE LIST Mon Sep 10 15:02:41 2001 PAGE 010
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
553 00325 04 .align ; End of master receive.
554 ;;;------------------------------------------------------------------------------
555 00326 rcv_nack_err: ;
556 00326 D812 Q mov.b #01h,R1L ; Master receive NO ACK.
557 00328 62 S jmp ms_r_end ;
558 ;;; -----------------------------------------------------------------------------
559 00329 04 .align ;
560 0032A rcv_end: ;
561 0032A D802 Q mov.b #00h,R1L ;
562 0032C ms_r_end: ;
563 0032C F57B01 W jsr make_stop ;
564 0032F B70000r Z mov.b #00h,m_iic ; Set I2C bus mode condition to wait mode stop to start cond
565 ;;; for C
566 00332 744F0000r push.b md_cnt ; ---\
567 00336 D802 Q mov.b #00h,R1L ; \
568 00338 FD000000r A jsr $iic_mr_end ; \____For C Code return.
569 0033C 74DF0000r pop.b md_cnt ; /
570 00340 B70000r Z mov.b #00h,md_cnt ; ___/
571 00343 F43D01 W jmp u2rcv_int_end ;
572 ;;; ===========================================================================
573 ;; Slave "Receive" ID byte "First Byte"
574 ;; ACK of "First ID byte" and send first data byte.
575 ;;; ===========================================================================
576 .align ;
577 00346 sl_rcv_1: ;
578 .if DEBUG == 1 ; ---DEBUG---
579 00346 7E9F8C1F bset 4,dp ; ---DEBUG---
580 .endif ; ---DEBUG---
581 0034A 7E8FB21B bclr 2,U2SMR2 ; Disable hold at 9th bit.
582 0034E 7E8F791F bclr 1,PD7 ;
583 00352 sl_r_l1: ;
584 00352 7EBF691F btst 1,P7 ; -- Wait for SCL to go high.
585 00356 6AFB jz sl_r_l1 ; -/
586 00358 C70A7803 S mov.b #0ah,U2MR ; Set standard clock input mode.
587 0035C 75CF7A03FF00 mov.w #0ffh,U2TB ; Init UART2 to dummy data and ACK
588 00362 7E9FB21B bset 2,U2SMR2 ; 9th bit low set "ACK".
589 00366 7E8F781F bclr 0,PD7 ; Set SDA pin to input.
590 ;
591 0036A 7EBF0000r btst 1,m_iic ; Test I2C bus mode condition for arbitration.
592 0036E 6A04 jz sl_rcv10 ; IF 0 jump to s1_rcv10.
593 00370 F51601 W jsr abt_lost ; Else, jump to abt_lost.
594 00373 sl_rcv10: ;
595 00373 7E9F0000r bset 7,sd_p ; Bit set 7th bit of Slave Data Counter.
596 00377 C7050000r S mov.b #05h,m_iic ; Set I2C bus mode condition to slave receive mode.
597 0037B F40501 W jmp u2rcv_int_end ;
598 ;;; ===========================================================================
599 ;; ACK Slave ID and start first transmit first data byte.
600 ;;; ===========================================================================
601 .align ;
602 0037E sl_snd_1: ;
603 .if DEBUG == 1 ; ---DEBUG---
604 0037E 7E9F8B1F bset 3,dp ; ---DEBUG---
605 .endif ; ---DEBUG---
606 00382 72F20000r mov.b sd_p,R1L ; Copy slave data counter to R1L.
607 00386 D803 Q mov.b #00h,R1H ; Init R1H.
608 00388 73F40000r mov.w slave_ram,A0 ; Copy slave ram start address to A0.
609 0038C A114 add.w R1,A0 ; Add slave data counter to slave ram start address.
610 0038E 7262 mov.b [A0],R1L ; Copy data pointed to by A0 to R1L.
611 00390 D813 Q mov.b #01h,R1H ; Set 9th bit NACK.
612 00392 A70000r inc.b sd_p ; Increment slave data counter.
613 00395 977F0000r S and.b #07fh,sd_p ; Set 8th bit of slave data counter to zero.
614 00399 7E8FB21B bclr 2,U2SMR2 ; Disable SCL clock.
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