📄 i2cbus.lst
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* M16C FAMILY ASSEMBLER * SOURCE LIST Mon Sep 10 15:02:41 2001 PAGE 006
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
311 0013D FD000000r A jsr $iic_mw_end ;
312 00141 63 S jmp stsp_common_master_end
313 ;; R
314 .align ;
315 00142 stsp_common_master10: ;
316 00142 FD000000r A jsr $iic_mr_end ; Jump to Master Data Receive End.
317 00146 stsp_common_master_end: ;
318 00146 74DF0000r pop.b md_cnt ; Pop Master Receive Data Count
319 0014A B70000r Z mov.b #00h,md_cnt ; Init Master Receive Data Count to zero.
320 ;;; ------------------------------------------------------------------------------
321 ;; Slave Command function
322 ;;; ------------------------------------------------------------------------------
323 0014D stsp_int_end: ;
324 ; bclr 3,U2RB+1 ; Reset Arbitration lost flag
325 0014D B70000r Z mov.b #00h,m_iic ; Init I2C bus mode condition register.
326 00150 74D2 pop.b R1L ; Return value.
327 .if DEBUG == 1 ; ---DEBUG---
328 00152 7E8F8D1F bclr 5,dp ; ---DEBUG---
329 .endif ; ---DEBUG---
330 00156 FB reit ;
331 ;;; ******************************************************************************
332 ;; UART2 RECV INTERRUPT.
333 ;;; ******************************************************************************
334 00157 04 .align ;
335 00158 u2rcv_int: ;
336 .if DEBUG == 1 ; --- DEBUG ---
337 00158 7E9F8E1F bset 6,dp ; --- DEBUG ---
338 .endif ; --- DEBUG ---
339 0015C EC48 pushm A0,R1 ; Push multiple registers on to stack.
340 0015E 7E8FB61B bclr 6,U2SMR2 ; Bit clear SDHI, SDA output enable.
341 00162 7EBF5302 btst 3,STSPIC ; Bit test for first byte.
342 00166 6A57 jz byte_n ; If not first byte jump.
343 ;; ------------------------------------------------------------------------------
344 ;; End of first byte process timing.
345 ;; ------------------------------------------------------------------------------
346 00168 7E8F5302 bclr 3,STSPIC ; Clear Stop Start interrupt request.
347 0016C 9F044A00 S or.b #STSPIPL,STSPIC ; Enable Stop Start interrupt.
348 00170 byte_1: ;
349 00170 7EBFFB1B btst 3,U2RB+1 ; Test for Arbitration.
350 00174 6810 jc slave_1 ; If Arbitration interrupt, jump.
351 ;
352 00176 master_1: ;
353 00176 E7020000r S cmp.b #02h,m_iic ; Test I2C bus mode condition register for master transmissi
354 0017A 6A69 jz ms_snd_1 ; if master jump.
355 0017C E7030000r S cmp.b #03h,m_iic ; Test I2C bus mode condition register for master receive mo
356 00180 6E04 * jz ms_rcv_1 ; if slave jump.
F41501
357 00185 slave_1: ;
358 00185 F57503 W jsr wait_20usec ; New counter delay July 1999 by Bruce Embry.
359 00188 73F17E03 mov.w U2RB,R1 ; Copy receive buffer to R1
360 0018C 76227F and.b #7fh,R1L ; Filter out bit number 7.
361 0018F C0F20000r cmp.b id_adr,R1L ; Compare SLAVE ID to ID value received.
362 00193 6A10 jeq sl_next ; Jump if ID's match.
363 ;
364 00195 7EBF0000r btst 1,m_iic ; Test I2C bus mode condition register for Master operation.
365 00199 6E04 * jz slave_taiki ; if 0 jump to slave_taiki.
F4C402
366 0019E F5E802 W jsr abt_lost ; Jump to abt_lost and return.
367 001A1 F4BE02 W jmp slave_taiki ; jump to slave_taiki.
368 .align ;
369 ;
370 001A4 sl_next: ;
* M16C FAMILY ASSEMBLER * SOURCE LIST Mon Sep 10 15:02:41 2001 PAGE 007
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
371 001A4 7E8FB31B bclr 3,U2SMR2 ; Disable SDA output stop bit.
372 001A8 97FCED03 S and.b #0fch,P7 ; Set SDA output to low "ACK" "Slave ID Address"
373 001AC 9F03EF03 S or.b #03h,PD7 ; Direction change to output
374 001B0 B77803 Z mov.b #00h,U2MR ; Disable I2C mode.
375 001B3 7EB108 btst 8,R1 ; Test received data for READ /WRITE mode.
376 001B6 6C04 * jc sl_snd_1 ; If slave READ, jump to transmit data function.
F4C501
377 001BB F48A01 W jmp sl_rcv_1 ; If slave WRITE, jump to slave receive data functio
378 ;;
379 001BE byte_n: ;
380 001BE E7000000r S cmp.b #00h,m_iic ; Test I2C bus mode condition register for "wait mode stop t
381 001C2 6E04 * jeq u2rcv_int_end ; IF equal jump to u2rcv_int_end.
F4BC02
382 001C7 7EBF0000r btst 1,m_iic ; Test I2C bus mode condition register for master operation.
383 001CB 6A0C jz slave_n ; Jump if slave operation.
384 ;
385 001CD master_n: ;
386 001CD 7EBF0000r btst 0,m_iic ; Test I2C bus mode condition register for write or read.
387 001D1 6C04 * jc ms_rcv_n ; Jump for master receive.
F40001
388 001D6 FE47 B jmp ms_snd_n ; Else, this is master write.
389 ;
390 001D8 slave_n: ;
391 001D8 7EBF0000r btst 0,m_iic ; Test I2C bus mode condition register for write or read.
392 001DC 6C04 * jc sl_rcv_n ; Jump for slave receive mode.
F4E901
393 001E1 F43602 W jmp sl_snd_n ; jump for slave transmission mode.
394 ;;; ===========================================================================
395 ;; Master Transmit 1st data byte
396 ;; Test for ID byte ACK ---> If true send 1st data byte
397 ;;; ===========================================================================
398 .align ;
399 001E4 ms_snd_1: ;
400 .if DEBUG == 1 ; --- DEBUG ---
401 001E4 7E9F891F bset 1,dp ; --- DEBUG ---
402 .endif ; --- DEBUG ---
403 001E8 73F40000r mov.w mw_data,A0 ; Copy transmit data address to A0.
404 001EC 7262 mov.b [A0],R1L ; Copy data -> by A0 to R1L.
405 001EE D813 Q mov.b #01h,R1H ; Set 9th bit high, future test for ACK/NACK.
406 001F0 C7837603 S mov.b #83h,U2SMR2 ; SCL output disable
407 001F4 ms_s_l1: ;
408 001F4 7EBF691F btst 1,P7 ; --- Wait for SCL == HIGH.
409 001F8 6AFB jz ms_s_l1 ; --/
410 001FA 7EBF681F btst 0,P7 ; Bit test for ACK.
411 001FE 6E77 jnz snd_nack_err_1 ; If no ACK, jump to snd_nack_err_1.
412 00200 731F7A03 mov.w R1,U2TB ; ACK received continue. move data to UART2 transmit buffer
413 00204 C78F7603 S mov.b #8fh,U2SMR2 ; Authorize master transmit on I2C bus.
414 00208 F5DB02 W jsr wait_2usec ; New counter delay July 1999 by Bruce Embry.
415 0020B 7E9FB51B bset 5,U2SMR2 ; Enable master transmit. Keep SCL low.
416 0020F 7E8FFB1B bclr 3,U2RB+1 ; Clear arbitration bit.
417 00213 F5DC02 W jsr wait_5usec ; New counter delay July 1999 by Bruce Embry
418 00216 7E8FB51B bclr 5,U2SMR2 ; Release SCL and start transmitting on I2C bus.
419 0021A F46602 W jmp u2rcv_int_end ; Jump to u2rcv_int_end.
420 ;;; ===========================================================================
421 ;; Master Transmit
422 ;; Test for data byte ACK --> Set for next data byte.
423 ;;; ===========================================================================
424 0021D 04 .align ;
425 0021E ms_snd_n: ;
426 .if DEBUG == 1 ; --- DEBUG ---
427 0021E 7E9F891F bset 1,dp ; --- DEBUG ---
428 .endif ; --- DEBUG ---
* M16C FAMILY ASSEMBLER * SOURCE LIST Mon Sep 10 15:02:41 2001 PAGE 008
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
429 00222 7EBFFB1B btst 3,U2RB+1 ; Test arbitration bit.
430 00226 6A07 jz ms_snd_n10 ; If arbitration bit is cleared, then jump to
431 00228 F55E02 W jsr abt_lost ; else jump arbitration bit is set jump to sub
432 0022B F43402 W jmp slave_taiki ; Jump to slave_taiki.
433 .align ;
434 0022E ms_snd_n10: ;
435 ;
436 0022E A70000r inc.b md_cnt ; Increment master data counter.
437 00231 72F20000r mov.b md_cnt,R1L ; Copy master data counter to R1L register.
438 00235 D803 Q mov.b #00h,R1H ; Init R1H register to 00.
439 00237 73F40000r mov.w mw_data,A0 ; Copy master write data address pointer to A0.
440 0023B A114 add.w R1,A0 ; Add data counter to data address.
441 0023D 7262 mov.b [A0],R1L ; Get data pointed to by A0 and copy to R1L
442 0023F D813 Q mov.b #01h,R1H ; Set 8th bit to 1, "Not ACK."
443 00241 C7837603 S mov.b #83h,U2SMR2 ; Set I2C bus to not enable.
444 00245 ms_s_ln: ;
445 00245 7EBF691F btst 1,P7 ; ---Wait for SCL to go high.
446 00249 6AFB jz ms_s_ln ; -/
447 0024B 7EBF681F btst 0,P7 ; Check SDA.
448 0024F 6E2A jnz snd_nack_err_n ; If SDA is high, this is NACK, jump to snd_nack_err_n.
449 00251 C0FF0000r0000r cmp.b md_cnt,mw_lng ; Else, ACK received, compare master data count to data length.
450 00257 6A26 jeq snd_end ; If all data has been sent, then jump to snd_end "
451 ; Else set up to send next data byte.
452 00259 731F7A03 mov.w R1,U2TB ; Copy next data byte to UART2 transmit buffer.
453 0025D C78F7603 S mov.b #8fh,U2SMR2 ; Enable transmit of start character.
454 00261 F58202 W jsr wait_2usec ; New counter delay July 1999 by Bruce Embry.
455 00264 7E9FB51B bset 5,U2SMR2 ; Set set SWC2, "SCL goes low."
456 00268 7E8FFB1B bclr 3,U2RB+1 ; Clear arbitration bit.
457 0026C F58902 W jsr wait_15usec ; New counter delay July 1999 by Bruce Embry
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