📄 sfr62_ass.inc
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tb0s .btequ 5,tabsr ; Timer B0 count start flagtb1s .btequ 6,tabsr ; Timer B1 count start flagtb2s .btequ 7,tabsr ; Timer B2 count start flag;;-------------------------------------------------------; Clock prescaler reset flag;-------------------------------------------------------cpsrf .equ 0381h;cpsr .btequ 7,cpsrf ; Clock prescaler reset flag;;-------------------------------------------------------; One-shot start flag;-------------------------------------------------------onsf .equ 0382h;ta0os .btequ 0,onsf ; Timer A0 one-shot start flagta1os .btequ 1,onsf ; Timer A1 one-shot start flagta2os .btequ 2,onsf ; Timer A2 one-shot start flagta3os .btequ 3,onsf ; Timer A3 one-shot start flagta4os .btequ 4,onsf ; Timer A4 one-shot start flagta0tgl .btequ 6,onsf ; Timer A0 event/trigger select bitta0tgh .btequ 7,onsf ;;;-------------------------------------------------------; Trigger select register;-------------------------------------------------------trgsr .equ 0383h;ta1tgl .btequ 0,trgsr ; Timer A1 event/trigger select bitta1tgh .btequ 1,trgsr ;ta2tgl .btequ 2,trgsr ; Timer A2 event/trigger select bitta2tgh .btequ 3,trgsr ;ta3tgl .btequ 4,trgsr ; Timer A3 event/trigger select bitta3tgh .btequ 5,trgsr ;ta4tgl .btequ 6,trgsr ; Timer A4 event/trigger select bitta4tgh .btequ 7,trgsr ;;;-------------------------------------------------------; Up/down flag;-------------------------------------------------------udf .equ 0384h;ta0ud .btequ 0,udf ; Timer A0 up/down flagta1ud .btequ 1,udf ; Timer A1 up/down flagta2ud .btequ 2,udf ; Timer A2 up/down flagta3ud .btequ 3,udf ; Timer A3 up/down flagta4ud .btequ 4,udf ; Timer A4 up/down flagta2p .btequ 5,udf ; Timer A2 two-phase pulse signal processing select bitta3p .btequ 6,udf ; Timer A3 two-phase pulse signal processing select bitta4p .btequ 7,udf ; Timer A4 two-phase pulse signal processing select bit;;-------------------------------------------------------; Timer;-------------------------------------------------------ta0 .equ 0386h ; Timer A0ta0l .equ ta0 ; Lowta0h .equ ta0+1 ; High;ta1 .equ 0388h ; Timer A1ta1l .equ ta1 ; Lowta1h .equ ta1+1 ; High;ta2 .equ 038ah ; Timer A2ta2l .equ ta2 ; Lowta2h .equ ta2+1 ; High;ta3 .equ 038ch ; Timer A3ta3l .equ ta3 ; Lowta3h .equ ta3+1 ; High;ta4 .equ 038eh ; Timer A4ta4l .equ ta4 ; Lowta4h .equ ta4+1 ; High;tb0 .equ 0390h ; Timer B0tb0l .equ tb0 ; Lowtb0h .equ tb0+1 ; High;tb1 .equ 0392h ; Timer B1tb1l .equ tb1 ; Lowtb1h .equ tb1+1 ; High;tb2 .equ 0394h ; TimerB2tb2l .equ tb2 ; Lowtb2h .equ tb2+1 ; High;ta0mr .equ 0396h ; Timer A0 mode registertmod0_ta0mr .btequ 0,ta0mr ; Operation mode select bittmod1_ta0mr .btequ 1,ta0mr ;mr0_ta0mr .btequ 2,ta0mr ;mr1_ta0mr .btequ 3,ta0mr ;mr2_ta0mr .btequ 4,ta0mr ;mr3_ta0mr .btequ 5,ta0mr ;tck0_ta0mr .btequ 6,ta0mr ; Count source select bittck1_ta0mr .btequ 7,ta0mr ;;ta1mr .equ 0397h ; Timer A1 mode registertmod0_ta1mr .btequ 0,ta1mr ; Operation mode select bittmod1_ta1mr .btequ 1,ta1mr ;mr0_ta1mr .btequ 2,ta1mr ;mr1_ta1mr .btequ 3,ta1mr ;mr2_ta1mr .btequ 4,ta1mr ;mr3_ta1mr .btequ 5,ta1mr ;tck0_ta1mr .btequ 6,ta1mr ; Count source select bittck1_ta1mr .btequ 7,ta1mr ;;ta2mr .equ 0398h ; Timer A2 mode registertmod0_ta2mr .btequ 0,ta2mr ; Operation mode select bittmod1_ta2mr .btequ 1,ta2mr ;mr0_ta2mr .btequ 2,ta2mr ;mr1_ta2mr .btequ 3,ta2mr ;mr2_ta2mr .btequ 4,ta2mr ;mr3_ta2mr .btequ 5,ta2mr ;tck0_ta2mr .btequ 6,ta2mr ; Count source select bittck1_ta2mr .btequ 7,ta2mr ;;ta3mr .equ 0399h ; Timer A3 mode registertmod0_ta3mr .btequ 0,ta3mr ; Operation mode select bittmod1_ta3mr .btequ 1,ta3mr ;mr0_ta3mr .btequ 2,ta3mr ;mr1_ta3mr .btequ 3,ta3mr ;mr2_ta3mr .btequ 4,ta3mr ;mr3_ta3mr .btequ 5,ta3mr ;tck0_ta3mr .btequ 6,ta3mr ; Count source select bittck1_ta3mr .btequ 7,ta3mr ;;ta4mr .equ 039ah ; Timer A4 mode registertmod0_ta4mr .btequ 0,ta4mr ; Operation mode select bittmod1_ta4mr .btequ 1,ta4mr ;mr0_ta4mr .btequ 2,ta4mr ;mr1_ta4mr .btequ 3,ta4mr ;mr2_ta4mr .btequ 4,ta4mr ;mr3_ta4mr .btequ 5,ta4mr ;tck0_ta4mr .btequ 6,ta4mr ; Count source select bittck1_ta4mr .btequ 7,ta4mr ;;tb0mr .equ 039bh ; Timer B0 mode registertmod0_tb0mr .btequ 0,tb0mr ; Operation mode select bittmod1_tb0mr .btequ 1,tb0mr ;mr0_tb0mr .btequ 2,tb0mr ;mr1_tb0mr .btequ 3,tb0mr ;mr2_tb0mr .btequ 4,tb0mr ;mr3_tb0mr .btequ 5,tb0mr ;tck0_tb0mr .btequ 6,tb0mr ; Count source select bittck1_tb0mr .btequ 7,tb0mr ;;tb1mr .equ 039ch ; Timer B1 mode registertmod0_tb1mr .btequ 0,tb1mr ; Operation mode select bittmod1_tb1mr .btequ 1,tb1mr ;mr0_tb1mr .btequ 2,tb1mr ;mr1_tb1mr .btequ 3,tb1mr ;mr2_tb1mr .btequ 4,tb1mr ;mr3_tb1mr .btequ 5,tb1mr ;tck0_tb1mr .btequ 6,tb1mr ; Count source select bittck1_tb1mr .btequ 7,tb1mr ;;tb2mr .equ 039dh ; Timer B2 mode registertmod0_tb2mr .btequ 0,tb2mr ; Operation mode select bittmod1_tb2mr .btequ 1,tb2mr ;mr0_tb2mr .btequ 2,tb2mr ;mr1_tb2mr .btequ 3,tb2mr ;mr2_tb2mr .btequ 4,tb2mr ;mr3_tb2mr .btequ 5,tb2mr ;tck0_tb2mr .btequ 6,tb2mr ; Count source select bittck1_tb2mr .btequ 7,tb2mr ;;;-------------------------------------------------------; UART0;-------------------------------------------------------u0mr .equ 03a0h ; UART0 transmit/receive mode registersmd0_u0mr .btequ 0,u0mr ; Serial I/O mode select bitsmd1_u0mr .btequ 1,u0mr ;smd2_u0mr .btequ 2,u0mr ;ckdir_u0mr .btequ 3,u0mr ; Internal/external clock select bitstps_u0mr .btequ 4,u0mr ; Stop bit length select bitpry_u0mr .btequ 5,u0mr ; Odd/even parity select bitprye_u0mr .btequ 6,u0mr ; Parity enable bitslep_u0mr .btequ 7,u0mr ; Sleep select bit;u0brg .equ 03a1h ; UART0 bit rate generator;u0tb .equ 03a2h ; UART0 transmit buffer registeru0tbl .equ u0tb ; Lowu0tbh .equ u0tb+1 ; High;u0c0 .equ 03a4h ; UART0 transmit/receive control register 0clk0_u0c0 .btequ 0,u0c0 ; BRG count source select bitclk1_u0c0 .btequ 1,u0c0 ; crs_u0c0 .btequ 2,u0c0 ; CTS/RTS function select bittxept_u0c0 .btequ 3,u0c0 ; Transmit register empty flagcrd_u0c0 .btequ 4,u0c0 ; CTS/RTS enable bitnch_u0c0 .btequ 5,u0c0 ; Data output select bitckpol_u0c0 .btequ 6,u0c0 ; CLK polarity select bituform_u0c0 .btequ 7,u0c0 ; Transfer format select bit;u0c1 .equ 03a5h ; UART0 transmit/receive control register 1te_u0c1 .btequ 0,u0c1 ; Transmit enable bitti_u0c1 .btequ 1,u0c1 ; Transmit buffer empty flagre_u0c1 .btequ 2,u0c1 ; Receive enable bitri_u0c1 .btequ 3,u0c1 ; Receive complete flag;u0rb .equ 03a6h ; UART0 receive buffer registeru0rbl .equ u0rb ; Lowu0rbh .equ u0rb+1 ; Highabt_u0rb .btequ 3,u0rbh ; Arbitrastion lost detecting flagoer_u0rb .btequ 4,u0rbh ; Overrun error flagfer_u0rb .btequ 5,u0rbh ; Framing error flagper_u0rb .btequ 6,u0rbh ; Parity error flagsum_u0rb .btequ 7,u0rbh ; Error sum flag;;-------------------------------------------------------; UART1 ;-------------------------------------------------------u1mr .equ 03a8h ; UART1 transmit/receive mode registersmd0_u1mr .btequ 0,u1mr ; Serial I/O mode select bitsmd1_u1mr .btequ 1,u1mr ;smd2_u1mr .btequ 2,u1mr ;ckdir_u1mr .btequ 3,u1mr ; Internal/external clock select bitstps_u1mr .btequ 4,u1mr ; Stop bit length select bitpry_u1mr .btequ 5,u1mr ; Odd/even parity select bitprye_u1mr .btequ 6,u1mr ; Parity enable bitslep_u1mr .btequ 7,u1mr ; Sleep select bit;u1brg .equ 03a9h ; UART1 bit rate generator;u1tb .equ 03aah ; UART1 transmit buffer registeru1tbl .equ u1tb ; Lowu1tbh .equ u1tb+1 ; High;u1c0 .equ 03ach ; UART1 transmit/receive control register 0clk0_u1c0 .btequ 0,u1c0 ; BRG count source select bitclk1_u1c0 .btequ 1,u1c0 ; crs_u1c0 .btequ 2,u1c0 ; CTS/RTS function select bittxept_u1c0 .btequ 3,u1c0 ; Transmit register empty flagcrd_u1c0 .btequ 4,u1c0 ; CTS/RTS disable bitnch_u1c0 .btequ 5,u1c0 ; Data output select bitckpol_u1c0 .btequ 6,u1c0 ; CLK polarity select bituform_u1c0 .btequ 7,u1c0 ; Transfer format select bit;u1c1 .equ 03adh ; UART1 transmit/receive control register 1te_u1c1 .btequ 0,u1c1 ; Transmit enable bitti_u1c1 .btequ 1,u1c1 ; Transmit buffer empty flagre_u1c1 .btequ 2,u1c1 ; Receive enable bitri_u1c1 .btequ 3,u1c1 ; Receive complete flag;u1rb .equ 03aeh ; UART1 receive registeru1rbl .equ u1rb ; Lowu1rbh .equ u1rb+1 ; Highabt_u1rb .btequ 3,u1rbh ; Arbitrastion lost detecting flagoer_u1rb .btequ 4,u1rbh ; Overrun error flagfer_u1rb .btequ 5,u1rbh ; Framing error flagper_u1rb .btequ 6,u1rbh ; Parity error flagsum_u1rb .btequ 7,u1rbh ; Error sum flag;ucon .equ 03b0h ; UART transmit/receive control register 2u0irs .btequ 0,ucon ; UART0 transmit interrupt cause selectbitu1irs .btequ 1,ucon ; UART1 transmit interrupt cause selectbitu0rrm .btequ 2,ucon ; UART0 continuous receive mode disable bitu1rrm .btequ 3,ucon ; UART1 continuous receive mode disable bitclkmd0 .btequ 4,ucon ; CLK/CLKS select bitclkmd1 .btequ 5,ucon ;rcsp .btequ 6,ucon ; Separate RTS/CTS bit;;-------------------------------------------------------; Flash memory control register 1;-------------------------------------------------------
fmr1 .equ 03b6h
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fmr13 .btequ 3,fmr1;-------------------------------------------------------; Flash memory control register 0;-------------------------------------------------------fmr0 .equ 03b7h;fmr00 .btequ 0,fmr0 ; RY/BY status bitfmr01 .btequ 1,fmr0 ; CPU rewrite mode select bitfmr02 .btequ 2,fmr0 ; Lock disable bitfmr03 .btequ 3,fmr0 ; Flash memory reset bit
fmr05 .btequ 5,fmr0 ; User ROM area select bit;;--------------------------------------------------------; DMA request cause select register;--------------------------------------------------------dm0sl .equ 03b8h ; DMA0 request cause select registerdsel0_dm0sl .btequ 0,dm0sl ; DMA request cause select bitdsel1_dm0sl .btequ 1,dm0sl ;dsel2_dm0sl .btequ 2,dm0sl ;dsel3_dm0sl .btequ 3,dm0sl ;dms_dm0sl .btequ 6,dm0sl ;dsr_dm0sl .btequ 7,dm0sl ; Software DMA request bit;dm1sl .equ 03bah ; DMA1 request cause select registerdsel0_dm1sl .btequ 0,dm1sl ; DMA request cause select bitdsel1_dm1sl .btequ 1,dm1sl ;dsel2_dm1sl .btequ 2,dm1sl ;dsel3_dm1sl .btequ 3,dm1sl ;dms_dm1sl .btequ 6,dm1sl ;dsr_dm1sl .btequ 7,dm1sl ; Software DMA request bit;;-------------------------------------------------------; CRC;-------------------------------------------------------crcd .equ 03bch ; CRC data registercrcdl .equ crcd ; Lowcrcdh .equ crcd+1 ; High;crcin .equ 03beh ; CRC input register;;-------------------------------------------------------; A-D, D-A;-------------------------------------------------------ad0 .equ 03c0h ; AD register 0ad0l .equ ad0 ; Lowad0h .equ ad0+1 ; High;ad1 .equ 03c2h ; AD register 1ad1l .equ ad1 ; Lowad1h .equ ad1+1 ; High;ad2 .equ 03c4h ; AD register 2⌨️ 快捷键说明
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