📄 sfr62_ass.inc
字号:
ir_s0tic .btequ 3,s0tic ; Interrupt request bit;s0ric .equ 0052h ; UART0 receive interrupt control registerilvl0_s0ric .btequ 0,s0ric ; Interrupt priority level select bitilvl1_s0ric .btequ 1,s0ric ;ilvl2_s0ric .btequ 2,s0ric ;ir_s0ric .btequ 3,s0ric ; Interrupt request bit;s1tic .equ 0053h ; UART1 transmit interrupt control registerilvl0_s1tic .btequ 0,s1tic ; Interrupt priority level select bitilvl1_s1tic .btequ 1,s1tic ;ilvl2_s1tic .btequ 2,s1tic ;ir_s1tic .btequ 3,s1tic ; Interrupt request bit;s1ric .equ 0054h ; UART1 receive interrupt control registerilvl0_s1ric .btequ 0,s1ric ; Interrupt priority level select bitilvl1_s1ric .btequ 1,s1ric ;ilvl2_s1ric .btequ 2,s1ric ;ir_s1ric .btequ 3,s1ric ; Interrupt request bit;ta0ic .equ 0055h ; Timer A0ilvl0_ta0ic .btequ 0,ta0ic ; Interrupt priority level select bitilvl1_ta0ic .btequ 1,ta0ic ;ilvl2_ta0ic .btequ 2,ta0ic ;ir_ta0ic .btequ 3,ta0ic ; Interrupt request bit;ta1ic .equ 0056h ; Timer A1ilvl0_ta1ic .btequ 0,ta1ic ; Interrupt priority level select bitilvl1_ta1ic .btequ 1,ta1ic ;ilvl2_ta1ic .btequ 2,ta1ic ;ir_ta1ic .btequ 3,ta1ic ; Interrupt request bit;ta2ic .equ 0057h ; Timer A2ilvl0_ta2ic .btequ 0,ta2ic ; Interrupt priority level select bitilvl1_ta2ic .btequ 1,ta2ic ;ilvl2_ta2ic .btequ 2,ta2ic ;ir_ta2ic .btequ 3,ta2ic ; Interrupt request bit;ta3ic .equ 0058h ; Timer A3ilvl0_ta3ic .btequ 0,ta3ic ; Interrupt priority level select bitilvl1_ta3ic .btequ 1,ta3ic ;ilvl2_ta3ic .btequ 2,ta3ic ;ir_ta3ic .btequ 3,ta3ic ; Interrupt request bit;ta4ic .equ 0059h ; Timer A4ilvl0_ta4ic .btequ 0,ta4ic ; Interrupt priority level select bitilvl1_ta4ic .btequ 1,ta4ic ;ilvl2_ta4ic .btequ 2,ta4ic ;ir_ta4ic .btequ 3,ta4ic ; Interrupt request bit;tb0ic .equ 005ah ; Timer B0ilvl0_tb0ic .btequ 0,tb0ic ; Interrupt priority level select bitilvl1_tb0ic .btequ 1,tb0ic ;ilvl2_tb0ic .btequ 2,tb0ic ;ir_tb0ic .btequ 3,tb0ic ; Interrupt request bit;tb1ic .equ 005bh ; Timer B1ilvl0_tb1ic .btequ 0,tb1ic ; Interrupt priority level select bitilvl1_tb1ic .btequ 1,tb1ic ;ilvl2_tb1ic .btequ 2,tb1ic ;ir_tb1ic .btequ 3,tb1ic ; Interrupt request bit;tb2ic .equ 005ch ; Timer B2ilvl0_tb2ic .btequ 0,tb2ic ; Interrupt priority level select bitilvl1_tb2ic .btequ 1,tb2ic ;ilvl2_tb2ic .btequ 2,tb2ic ;ir_tb2ic .btequ 3,tb2ic ; Interrupt request bit;int0ic .equ 005dh ; INT0ilvl0_int0ic .btequ 0,int0ic ; Interrupt priority level select bitilvl1_int0ic .btequ 1,int0ic ;ilvl2_int0ic .btequ 2,int0ic ;ir_int0ic .btequ 3,int0ic ; Interrupt request bitpol_int0ic .btequ 4,int0ic ; Polarity select bit;int1ic .equ 005eh ; INT1ilvl0_int1ic .btequ 0,int1ic ; Interrupt priority level select bitilvl1_int1ic .btequ 1,int1ic ;ilvl2_int1ic .btequ 2,int1ic ;ir_int1ic .btequ 3,int1ic ; Interrupt request bitpol_int1ic .btequ 4,int1ic ; Polarity select bit;int2ic .equ 005fh ; INT2ilvl0_int2ic .btequ 0,int2ic ; Interrupt priority level select bitilvl1_int2ic .btequ 1,int2ic ;ilvl2_int2ic .btequ 2,int2ic ;ir_int2ic .btequ 3,int2ic ; Interrupt request bitpol_int2ic .btequ 4,int2ic ; Polarity select bit;;-------------------------------------------------------; additional timer B3,B4,B5;-------------------------------------------------------tbsr .equ 0340htb3s .btequ 5,tbsrtb4s .btequ 6,tbsrtb5s .btequ 7,tbsr;ta11 .equ 0342hta11l .equ ta11ta11h .equ ta11+1;ta21 .equ 0344hta21l .equ ta21ta21h .equ ta21+1;ta41 .equ 0346hta41l .equ ta41ta41h .equ ta41+1;invc0 .equ 0348hinv00 .btequ 0,invc0inv01 .btequ 1,invc0inv02 .btequ 2,invc0inv03 .btequ 3,invc0inv04 .btequ 4,invc0inv05 .btequ 5,invc0inv06 .btequ 6,invc0inv07 .btequ 7,invc0;invc1 .equ 0349hinv10 .btequ 0,invc1inv11 .btequ 1,invc1inv12 .btequ 2,invc1;idb0 .equ 034ahdu0 .btequ 0,idb0dub0 .btequ 1,idb0dv0 .btequ 2,idb0dvb0 .btequ 3,idb0dw0 .btequ 4,idb0dwb0 .btequ 5,idb0;idb1 .equ 034bhdu1 .btequ 0,idb1dub1 .btequ 1,idb1dv1 .btequ 2,idb1dvb1 .btequ 3,idb1dw1 .btequ 4,idb1dwb1 .btequ 5,idb1;dtt .equ 034ch;ictb2 .equ 034dh;tb3 .equ 0350htb3l .equ tb3tb3h .equ tb3+1;tb4 .equ 0352htb4l .equ tb4tb4h .equ tb4+1;tb5 .equ 0354htb5l .equ tb5tb5h .equ tb5+1;tb3mr .equ 035bhtmod0_tb3mr .btequ 0,tb3mr ; Operation mode select bittmod1_tb3mr .btequ 1,tb3mr ;mr0_tb3mr .btequ 2,tb3mr ;mr1_tb3mr .btequ 3,tb3mr ;mr2_tb3mr .btequ 4,tb3mr ;mr3_tb3mr .btequ 5,tb3mr ;tck0_tb3mr .btequ 6,tb3mr ; Count source select bittck1_tb3mr .btequ 7,tb3mr ;;tb4mr .equ 035chtmod0_tb4mr .btequ 0,tb4mr ; Operation mode select bittmod1_tb4mr .btequ 1,tb4mr ;mr0_tb4mr .btequ 2,tb4mr ;mr1_tb4mr .btequ 3,tb4mr ;mr2_tb4mr .btequ 4,tb4mr ;mr3_tb4mr .btequ 5,tb4mr ;tck0_tb4mr .btequ 6,tb4mr ; Count source select bittck1_tb4mr .btequ 7,tb4mr ;;tb5mr .equ 035dhtmod0_tb5mr .btequ 0,tb5mr ; Operation mode select bittmod1_tb5mr .btequ 1,tb5mr ;mr0_tb5mr .btequ 2,tb5mr ;mr1_tb5mr .btequ 3,tb5mr ;mr2_tb5mr .btequ 4,tb5mr ;mr3_tb5mr .btequ 5,tb5mr ;tck0_tb5mr .btequ 6,tb5mr ; Count source select bittck1_tb5mr .btequ 7,tb5mr ;;;-------------------------------------------------------; Interrupt request cause select register;-------------------------------------------------------ifsr .equ 035fhifsr0 .btequ 0,ifsrifsr1 .btequ 1,ifsrifsr2 .btequ 2,ifsrifsr3 .btequ 3,ifsrifsr4 .btequ 4,ifsrifsr5 .btequ 5,ifsrifsr6 .btequ 6,ifsrifsr7 .btequ 7,ifsr;;-------------------------------------------------------; SI/O 3;-------------------------------------------------------s3trr .equ 0360hs3trrl .equ s3trrs3trrh .equ s3trr+1;s3c .equ 0362hsm30 .btequ 0,s3csm31 .btequ 1,s3csm32 .btequ 2,s3csm33 .btequ 3,s3csm35 .btequ 5,s3csm36 .btequ 6,s3csm37 .btequ 7,s3c;s3brg .equ 0363h;;-------------------------------------------------------; SI/O 4;-------------------------------------------------------s4trr .equ 0364hs4trrl .equ s4trrs4trrh .equ s4trr+1;s4c .equ 0366hsm40 .btequ 0,s4csm41 .btequ 1,s4csm42 .btequ 2,s4csm43 .btequ 3,s4csm45 .btequ 5,s4csm46 .btequ 6,s4csm47 .btequ 7,s4c;s4brg .equ 0367h;;-------------------------------------------------------; UART2;-------------------------------------------------------u2smr3 .equ 0375h ; UART2 Special Mode register 3(Ver.1.04)dl0_u2smr3 .btequ 5,u2smr3 ; SDA digital delay setup bitdl1_u2smr3 .btequ 6,u2smr3 ;dl2_u2smr3 .btequ 7,u2smr3 ;;u2smr2 .equ 0376h ; UART2 Special Mode register 2iicm2_u2smr2 .btequ 0,u2smr2 ; IIC mode selection bit2csc_u2smr2 .btequ 1,u2smr2 ; Clock-synchronous bitswc_u2smr2 .btequ 2,u2smr2 ; SCL wait output bitals_u2smr2 .btequ 3,u2smr2 ; SDA output stop bitstac_u2smr2 .btequ 4,u2smr2 ; UART2 initialization bitswc2_u2smr2 .btequ 5,u2smr2 ; SCL wait output bit 2sdhi_u2smr2 .btequ 6,u2smr2 ; SDA output disable bitshtc_u2smr2 .btequ 7,u2smr2 ; Start/stop condition control bit;u2smr .equ 0377h ; UART2 Special Mode register iicm_u2smr .btequ 0,u2smr ; IIC mode selection bit abc_u2smr .btequ 1,u2smr ; Arbitration lost detecting flag control bitbbs_u2smr .btequ 2,u2smr ; Bus busy flaglsyn_u2smr .btequ 3,u2smr ; SCLL sync output enable bitabscs_u2smr .btequ 4,u2smr ; Bus collision detect sampring clock select bitacse_u2smr .btequ 5,u2smr ; Auto clear function select bit of transmit enable bitsss_u2smr .btequ 6,u2smr ; Transmit start condition select bitsdds_u2smr .btequ 7,u2smr ; SDA digital delay select bit(Ver.1.04);u2mr .equ 0378h ; UART2 transmit/receive mode registersmd0_u2mr .btequ 0,u2mr ; Serial I/O mode select bitsmd1_u2mr .btequ 1,u2mr ;smd2_u2mr .btequ 2,u2mr ;ckdir_u2mr .btequ 3,u2mr ; Internal/external Clock select bitstps_u2mr .btequ 4,u2mr ; Stop bit length selectbitpry_u2mr .btequ 5,u2mr ; Odd/even parity select bitprye_u2mr .btequ 6,u2mr ; Parity enable bitiopol_u2mr .btequ 7,u2mr ; TxD,RxD I/O polarity reverse bit;u2brg .equ 0379h ; UART2 bit rate generator;u2tb .equ 037ah ; UART2 transmit buffer registeru2tbl .equ u2tb ; Lowu2tbh .equ u2tb+1 ; High;u2c0 .equ 037ch ; UART2 transmit/receive control register 0clk0_u2c0 .btequ 0,u2c0 ; BRG count source select bitclk1_u2c0 .btequ 1,u2c0 ;crs_u2c0 .btequ 2,u2c0 ; CTS/RTS function select bittxept_u2c0 .btequ 3,u2c0 ; Transmit register empty flagcrd_u2c0 .btequ 4,u2c0 ; CTS/RTS disable bitckpol_u2c0 .btequ 6,u2c0 ; CLK polarity select bituform_u2c0 .btequ 7,u2c0 ; Transfer format select bit;u2c1 .equ 037dh ; UART2 transmit/receive control register 1te_u2c1 .btequ 0,u2c1 ; Transmit enable bitti_u2c1 .btequ 1,u2c1 ; Transmit buffer empty flagre_u2c1 .btequ 2,u2c1 ; Receive enable bitri_u2c1 .btequ 3,u2c1 ; Receive complete flagu2irs .btequ 4,u2c1 ; UART2 transmit interrupt cause select bitu2rrm .btequ 5,u2c1 ; UART2 continuous receive mode enable bitu2lch .btequ 6,u2c1 ; Data logic select bitu2ere .btequ 7,u2c1 ; Error signal output enable bitu2irs_u2c1 .btequ 4,u2c1u2rrm_u2c1 .btequ 5,u2c1u2lch_u2c1 .btequ 6,u2c1u2ere_u2c1 .btequ 7,u2c1;u2rb .equ 037eh ; UART2 receive buffer registeru2rbl .equ u2rb ; Lowu2rbh .equ u2rb+1 ; Highabt_u2rb .btequ 3,u2rbh ; Arbitrastion lost detecting flagoer_u2rb .btequ 4,u2rbh ; Overrun error flagfer_u2rb .btequ 5,u2rbh ; Framing error flagper_u2rb .btequ 6,u2rbh ; Parity error flagsum_u2rb .btequ 7,u2rbh ; Error sum flag;;-------------------------------------------------------; Count start flag;-------------------------------------------------------tabsr .equ 0380h;ta0s .btequ 0,tabsr ; Timer A0 count start flagta1s .btequ 1,tabsr ; Timer A1 count start flagta2s .btequ 2,tabsr ; Timer A2 count start flagta3s .btequ 3,tabsr ; Timer A3 count start flagta4s .btequ 4,tabsr ; Timer A4 count start flag⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -