📄 sfr62.h
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#pragma ADDRESS ad1_addr 03c2H /* A-D register 1 */
#pragma ADDRESS ad2_addr 03c4H /* A-D register 2 */
#pragma ADDRESS ad3_addr 03c6H /* A-D register 3 */
#pragma ADDRESS ad4_addr 03c8H /* A-D register 4 */
#pragma ADDRESS ad5_addr 03caH /* A-D register 5 */
#pragma ADDRESS ad6_addr 03ccH /* A-D register 6 */
#pragma ADDRESS ad7_addr 03ceH /* A-D register 7 */
#pragma ADDRESS adcon2_addr 03d4H /* A-D control register 2 */
#pragma ADDRESS adcon0_addr 03d6H /* A-D control register 0 */
#pragma ADDRESS adcon1_addr 03d7H /* A-D control register 1 */
#pragma ADDRESS da0_addr 03d8H /* D-A register 0 */
#pragma ADDRESS da1_addr 03daH /* D-A register 1 */
#pragma ADDRESS dacon_addr 03dcH /* D-A control register */
#pragma ADDRESS p0_addr 03e0H /* Port P0 */
#pragma ADDRESS p1_addr 03e1H /* Port P1 */
#pragma ADDRESS pd0_addr 03e2H /* Port P0 direction register */
#pragma ADDRESS pd1_addr 03e3H /* Port P1 direction register */
#pragma ADDRESS p2_addr 03e4H /* Port P2 */
#pragma ADDRESS p3_addr 03e5H /* Port P3 */
#pragma ADDRESS pd2_addr 03e6H /* Port P2 direction register */
#pragma ADDRESS pd3_addr 03e7H /* Port P3 direction register */
#pragma ADDRESS p4_addr 03e8H /* Port P4 */
#pragma ADDRESS p5_addr 03e9H /* Port P5 */
#pragma ADDRESS pd4_addr 03eaH /* Port P4 direction register */
#pragma ADDRESS pd5_addr 03ebH /* Port P5 direction register */
#pragma ADDRESS p6_addr 03ecH /* Port P6 */
#pragma ADDRESS p7_addr 03edH /* Port P7 */
#pragma ADDRESS pd6_addr 03eeH /* Port P6 direction register */
#pragma ADDRESS pd7_addr 03efH /* Port P7 direction register */
#pragma ADDRESS p8_addr 03f0H /* Port P8 */
#pragma ADDRESS p9_addr 03f1H /* Port P9 */
#pragma ADDRESS pd8_addr 03f2H /* Port P8 direction register */
#pragma ADDRESS pd9_addr 03f3H /* Port P9 direction register */
#pragma ADDRESS p10_addr 03f4H /* Port P10 */
#pragma ADDRESS pd10_addr 03f6H /* Port P10 direction register */
#pragma ADDRESS pur0_addr 03fcH /* Pull-up control register 0 */
#pragma ADDRESS pur1_addr 03fdH /* Pull-up control register 1 */
#pragma ADDRESS pur2_addr 03feH /* Pull-up control register 2 */
#pragma ADDRESS pcr_addr 03ffH /* Port control register */
/********************************************************
* declare SFR char *
********************************************************/
unsigned char da0_addr; /* D-A register 0 */
#define da0 da0_addr
unsigned char da1_addr; /* D-A register 1 */
#define da1 da1_addr
/********************************************************
* declare SFR bit *
********************************************************/
struct bit_def {
char b0:1;
char b1:1;
char b2:1;
char b3:1;
char b4:1;
char b5:1;
char b6:1;
char b7:1;
};
union byte_def{
struct bit_def bit;
char byte;
};
/*------------------------------------------------------
Processor mode register 0 bit
------------------------------------------------------*/
union byte_def pm0_addr;
#define pm0 pm0_addr.byte
#define pm00 pm0_addr.bit.b0 /* Processor mode bit */
#define pm01 pm0_addr.bit.b1 /* Processor mode bit */
#define pm02 pm0_addr.bit.b2 /* R/W mode select bit*/
#define pm03 pm0_addr.bit.b3 /* Software reset bit */
#define pm04 pm0_addr.bit.b4 /* Multiplexed bus space select bit */
#define pm05 pm0_addr.bit.b5 /* Multiplexed bus space select bit */
#define pm06 pm0_addr.bit.b6 /* Port P40~P43 function select bit */
#define pm07 pm0_addr.bit.b7 /* BCLK output disable bit */
/*------------------------------------------------------
Processor mode register 1 bit
------------------------------------------------------*/
union byte_def pm1_addr;
#define pm1 pm1_addr.byte
#define pm13 pm1_addr.bit.b3 /* Intermal reserved area expansion bit (62) */
#define pm14 pm1_addr.bit.b4 /* Memory area expansion bit (62) */
#define pm15 pm1_addr.bit.b5 /* (62) */
#define pm16 pm1_addr.bit.b6 /* Reserved bit */
#define pm17 pm1_addr.bit.b7 /* Wait bit */
/*------------------------------------------------------
System clock control register 0
------------------------------------------------------*/
union byte_def cm0_addr;
#define cm0 cm0_addr.byte
#define cm00 cm0_addr.bit.b0 /* Clock output function select bit */
#define cm01 cm0_addr.bit.b1 /* Clock output function select bit */
#define cm02 cm0_addr.bit.b2 /* WAIT peripheral function clock stop bit */
#define cm03 cm0_addr.bit.b3 /* Xcin-Xcout drive capacity select bit */
#define cm04 cm0_addr.bit.b4 /* Port Xc select bit */
#define cm05 cm0_addr.bit.b5 /* Main clock stop bit */
#define cm06 cm0_addr.bit.b6 /* Main clock division select bit 0 */
#define cm07 cm0_addr.bit.b7 /* System clock select bit */
/*------------------------------------------------------
System clock control register 1
------------------------------------------------------*/
union byte_def cm1_addr;
#define cm1 cm1_addr.byte
#define cm10 cm1_addr.bit.b0 /* All clock stop control bit */
#define cm15 cm1_addr.bit.b5 /* Xin-Xout drive capacity select bit */
#define cm16 cm1_addr.bit.b6 /* Main clock division select bit */
#define cm17 cm1_addr.bit.b7 /* Main clock division select bit */
/*------------------------------------------------------
Chip select control register
------------------------------------------------------*/
union byte_def csr_addr;
#define csr csr_addr.byte
#define cs0 csr_addr.bit.b0 /* CS0 output enable bit */
#define cs1 csr_addr.bit.b1 /* CS1 output enable bit */
#define cs2 csr_addr.bit.b2 /* CS2 output enable bit */
#define cs3 csr_addr.bit.b3 /* CS3 output enable bit */
#define cs0w csr_addr.bit.b4 /* CS0 wait bit */
#define cs1w csr_addr.bit.b5 /* CS1 wait bit */
#define cs2w csr_addr.bit.b6 /* CS2 wait bit */
#define cs3w csr_addr.bit.b7 /* CS3 wait bit */
/*------------------------------------------------------
Addrese match interrupt enable register
------------------------------------------------------*/
union byte_def aier_addr;
#define aier aier_addr.byte
#define aier0 aier_addr.bit.b0 /* Addrese match interrupt 0 enable bit */
#define aier1 aier_addr.bit.b1 /* Addrese match interrupt 1 enable bit */
/*------------------------------------------------------
Protect register
------------------------------------------------------*/
union byte_def prcr_addr;
#define prcr prcr_addr.byte
#define prc0 prcr_addr.bit.b0 /* Enables writing to system clock control register 0,1 */
#define prc1 prcr_addr.bit.b1 /* Enables writing to processor mode register 0,1 */
#define prc2 prcr_addr.bit.b2 /* Enables writing to port P9 direction register */
/*------------------------------------------------------
Data bank register (62)
------------------------------------------------------*/
union byte_def dbr_addr;
#define dbr dbr_addr.byte
#define ofs dbr_addr.bit.b2 /* Offset bit */
#define bsr0 dbr_addr.bit.b3 /* Bank select bit 0 */
#define bsr1 dbr_addr.bit.b4 /* Bank select bit 1 */
#define bsr2 dbr_addr.bit.b5 /* Bank select bit 2 */
/*------------------------------------------------------
Watchdog timer start register
------------------------------------------------------*/
union byte_def wdts_addr;
#define wdts wdts_addr.byte
/*------------------------------------------------------
CRC input register
------------------------------------------------------*/
union byte_def crcin_addr;
#define crcin crcin_addr.byte
/*------------------------------------------------------
Watchdog timer control register
------------------------------------------------------*/
union byte_def wdc_addr;
#define wdc wdc_addr.byte
#define wdc5 wdc_addr.bit.b5
#define wdc6 wdc_addr.bit.b6
#define wdc7 wdc_addr.bit.b7 /* Prescaler select bit */
/*------------------------------------------------------
Count start flag
------------------------------------------------------*/
union byte_def tabsr_addr;
#define tabsr tabsr_addr.byte
#define ta0s tabsr_addr.bit.b0 /* Timer A0 count start flag */
#define ta1s tabsr_addr.bit.b1 /* Timer A1 count start flag */
#define ta2s tabsr_addr.bit.b2 /* Timer A2 count start flag */
#define ta3s tabsr_addr.bit.b3 /* Timer A3 count start flag */
#define ta4s tabsr_addr.bit.b4 /* Timer A4 count start flag */
#define tb0s tabsr_addr.bit.b5 /* Timer B0 count start flag */
#define tb1s tabsr_addr.bit.b6 /* Timer B1 count start flag */
#define tb2s tabsr_addr.bit.b7 /* Timer B2 count start flag */
/*------------------------------------------------------
Timer B3,4,5 Count start flag (62)
------------------------------------------------------*/
union byte_def tbsr_addr;
#define tbsr tbsr_addr.byte
#define tb3s tbsr_addr.bit.b5 /* Timer B3 count start flag */
#define tb4s tbsr_addr.bit.b6 /* Timer B4 count start flag */
#define tb5s tbsr_addr.bit.b7 /* Timer B5 count start flag */
/*------------------------------------------------------
Three-phase PWM control regester 0 (62)
------------------------------------------------------*/
union byte_def invc0_addr;
#define invc0 invc0_addr.byte
#define inv00 invc0_addr.bit.b0 /* (62) */
#define inv01 invc0_addr.bit.b1 /* (62) */
#define inv02 invc0_addr.bit.b2 /* (62) */
#define inv03 invc0_addr.bit.b3 /* (62) */
#define inv04 invc0_addr.bit.b4 /* (62) */
#define inv05 invc0_addr.bit.b5 /* (62) */
#define inv06 invc0_addr.bit.b6 /* (62) */
#define inv07 invc0_addr.bit.b7 /* (62) */
/*------------------------------------------------------
Three-phase PWM control regester 1 (62)
------------------------------------------------------*/
union byte_def invc1_addr;
#define invc1 invc1_addr.byte
#define inv10 invc1_addr.bit.b0 /* (62) */
#define inv11 invc1_addr.bit.b1 /* (62) */
#define inv12 invc1_addr.bit.b2 /* (62) */
#define inv14 invc1_addr.bit.b4 /* Reserved bit */
/*------------------------------------------------------
Three-phase output buffer register 0 (62)
------------------------------------------------------*/
union byte_def idb0_addr;
#define idb0 idb0_addr.byte
#define du0 idb0_addr.bit.b0 /* (62) */
#define dub0 idb0_addr.bit.b1 /* (62) */
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