📄 hcancont.c51
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unsigned int nr_of_trials = 0;
unsigned int mask;
mask = can_get_obj_mask (obj_adr);
do{
nr_of_trials++;
if (nr_of_trials > NBR_OF_SEND_TRIALS){
fcan_reg.r.transmit_request_set &= ~mask;
return FALSE;
}
} while ( (fcan_reg.r.transmit_request_set & mask) == mask );
return TRUE;
}
#pragma eject
/*---------------------------------------------------------------------*
* E X P O R T I E R T E P R O Z E D U R E N *
*---------------------------------------------------------------------*/
/*---------------------------------------------------------------------*
* C _ H W _ I N I T
*---------------------------------------------------------------------*
* Funktion:
* Grundinitialisierung des Siemens 81C91 CAN-Controllers.
* F乺 diese Operation wird der CAN-Controller angehalten.
* Er muss danach mit C_START wieder neu gestartet werden.
*
* init_mode = 1
* reset_request = 1
* warte bis reset_request = 1
*
* bit_length_1 = bit_length_1_reg
* bit_length_2 = bit_length_2_reg
* output_control = output_control_reg
* sleep_and_br_prescale = baud_rate_prescaler_reg
*
* receive_interrupt_mask = 0x0000
* can_disable_interrupts()
* interrupt_reg = 0x0000
*
* control = 0x00
* if sleep_and_br_prescale(bit 6) = 1
* control.SME = 1
*
* clock_control.cc = 0x07; fosc/14
*
* tr_check_error_counter.tcec = 0
* tr_check_data = 0
* transmit_request_reset = 0x0000
* time_stamp_counter = 0x00
*
* f乺 alle Objekte :
* descriptor.id = 0x07FF
* descriptor.rtr = 0
* descriptor.dlc = 0
* Daten = 0
*
*---------------------------------------------------------------------*
* Parameter:
*
* Bit-Length Register 1 :
* ---------------------------------------------
* SAM TS2.2 TS2.1 TS2.0 TS1.3 TS1.2 TS1.1 TS1.0
*
* TSEG1 =(TS1 +1)*fscl
* TSEG2 =(TS2 +1)*fscl
*
* Bit-Length Register 2 :
* ---------------------------------------------
* IPOL DI ----- ---- ----- SIM SJW.1 SJW.2
*
* SJWidth = (SJW + 1)*fscl
* SIM = 1
*
* sleep_and_br_prescale : sets bits BRPX( Bit 0.. Bit 5) of Baud rate reg.
* and SME (Bit 6) of Control reg.
* ---------------------------------------
* Baud rate prescaler reg.
* ---- --- BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
* Control reg.
* ---- SME ---- ---- ---- ---- ---- ----
*
*
* fscl = (BRP + 1)*2*fosc (fosc = 1 / fcrystal )
* fscl = (BRP + 1)*(2 / fcrystal)
*
* Bit length :
* fbl = TSEG1 + TSEG2 + 1 fscl
* Baaud rate :
* BR = fcrystal / ( 2*(BRP +1)*(TS1 + TS2 + 3))
*
*
* Returnwert : TRUE -> OK
* FALSE -> wenn reset_request bleibt = 1
*
*---------------------------------------------------------------------*/
byte c_hw_init (byte bit_length_1_reg,
byte bit_length_2_reg,
byte output_control_reg,
byte sleep_and_br_prescale)
{
byte inx,inx1;
fcan_reg.r.bit_length_1 = bit_length_1_reg;
fcan_reg.r.bit_length_2 = bit_length_2_reg;
fcan_reg.r.output_control = output_control_reg;
fcan_reg.r.baud_rate_prescaler = sleep_and_br_prescale & 0x3F;
fcan_reg.r.receive_interrupt_mask = 0x0000;
can_disable_interrupts();
fcan_reg.r.interrupt_reg.receive_interrupt = 0;
fcan_reg.r.interrupt_reg.transmit_interrupt = 0;
fcan_reg.r.interrupt_reg.warnig_level_interrupt = 0;
fcan_reg.r.interrupt_reg.remote_frame_interrupt = 0;
fcan_reg.r.interrupt_reg.wakeup_interrupt = 0;
fcan_reg.r.interrupt_reg.buss_off_interrupt = 0;
fcan_reg.r.interrupt_reg.error_passive_interrupt = 0;
fcan_reg.r.interrupt_reg.tr_check_interrupt = 0;
fcan_reg.r.control.monitor_mode = 0;
fcan_reg.r.control.tr_check_enable = 0;
fcan_reg.r.control.time_stamp_overflow = 0;
fcan_reg.r.control.time_stamp_prescaler = 0;
fcan_reg.r.control.time_stamp_test = 0;
fcan_reg.r.control.input_monitor_rx = 0;
if (sleep_and_br_prescale & 0x40 == 0x40){
fcan_reg.r.control.sleep_mode_enable = 1;
}
else{
fcan_reg.r.control.sleep_mode_enable = 0;
}
fcan_reg.r.clock_control.cc = 0x80;
fcan_reg.r.clock_control.cc = 0x07; /* fosc/14 */
fcan_reg.r.tr_check_error_counter.tcec = 0;
fcan_reg.r.tr_check_data = 0;
fcan_reg.r.transmit_request_reset = 0x0000;
fcan_reg.r.time_stamp_counter = 0x0000;
for (inx = 0; inx <= 15; inx++){
fcan_reg.r.descriptor[inx].id = 0x7FF;
fcan_reg.r.descriptor[inx].rtr = 0;
fcan_reg.r.descriptor[inx].dlc = 0;
for (inx1 = 0; inx1 <= 7; inx1++){
fcan_reg.r.message[inx].datas[inx1] = 0;
}
}
return TRUE;
}
/*---------------------------------------------------------------------*
* C _ I N I T _ C L O C K_C O N T _ R E G
*---------------------------------------------------------------------*
* Funktion:
* Initialisierung des CLOCK_CONTROL-REGISTERS des 81C91
*
*---------------------------------------------------------------------*
* Parameter:
*
* clock_cont_reg : Inhalt des 81C91 Clock_Control-Registers
*
*---------------------------------------------------------------------*/
void c_init_clock_cont_reg (byte clock_cont_reg)
{
fcan_reg.r.clock_control.cc = 0x80;
fcan_reg.r.clock_control.cc = clock_cont_reg & 0x0F;
}
/*---------------------------------------------------------------------*
* C _ I N I T _ O B J
*---------------------------------------------------------------------*
* Funktion:
* Definiert an der internen CAN-Controller Adresse BUF_ADR ein
* neues CAN-Objekt. Der CAN-Controller wird f乺 diese Operation
* angehalten, er muss danach mit C_START wieder neu gestartet
* werden.
*
* descriptor.dlc= data_len
* descriptor.id= ident
*
* transmit_request_set &= ~mask;
* receive_ready &= ~mask;
*
* wenn nur Data senden
* descriptor.rtr = 0
* receive_interrupt_mask &= ~mask;
* wenn remote senden und Antwort-Data empfangen
* descriptor.rtr = 0
* receive_interrupt_mask |= mask;
* wenn nur Data empfangen
* descriptor.rtr = 0
* receive_interrupt_mask |= mask;
* wenn Remote empfangen und Answer-Daten senden
* receive_interrupt_mask &= ~mask;
* descriptor.rtr = 1
*
*
*---------------------------------------------------------------------*
*
* Parameter:
*
* ident : Identifier des zu definierenden Objektes
* (0 .. 7FF)
* data_len : Anzahl Datenbytes des Objektes (0 .. 8)
* obj_typ : Genaue Beschreibung der Objektart :
* D_REC (0) : Receive data frame
* D_SEND (1) : Send data frame
* D_SEND_R_REC (2) : send data after remote recieving
* D_REC_R_SEND (3) : send remote frame
* obj_adr : Interne Start-Adresse des Objektes im CAN-Controller,
* das erste Objekt beginnt beim 81C91 bei der Adresse 80H.
*
*---------------------------------------------------------------------*/
void c_init_obj (unsigned int ident,
byte data_len,
byte obj_typ,
byte obj_adr
)
{
unsigned int mask;
byte obj_inx;
mask = can_get_obj_mask (obj_adr);
obj_inx = can_get_obj_inx (obj_adr);
fcan_reg.r.descriptor[obj_inx].dlc = data_len;
fcan_reg.r.descriptor[obj_inx].id = ident;
fcan_reg.r.transmit_request_set &= ~mask;
fcan_reg.r.receive_ready &= ~mask;
switch (obj_typ){
/* wenn nur Data senden */
case D_SEND :
fcan_reg.r.descriptor[obj_inx].rtr = 0;
/* keine receive interrupt */
fcan_reg.r.receive_interrupt_mask &= ~mask;
break;
/* wenn remote senden und Antwort-Data empfangen */
case D_REC_R_SEND :
fcan_reg.r.descriptor[obj_inx].rtr = 0;
/* receive interrupt */
fcan_reg.r.receive_interrupt_mask |= mask;
break;
/* wenn nur Data empfangen */
case D_REC :
fcan_reg.r.descriptor[obj_inx].rtr = 0;
/* receive interrupt */
fcan_reg.r.receive_interrupt_mask |= mask;
break;
/* wenn Remote empfangen und Answer-Daten senden */
case D_SEND_R_REC :
fcan_reg.r.descriptor[obj_inx].rtr = 1;
/* keine receive interrupt */
fcan_reg.r.receive_interrupt_mask &= ~mask;
break;
}
}
/*---------------------------------------------------------------------*
* C _ S T A R T
*---------------------------------------------------------------------*
* Funktion: 0k
* Starten des CAN-Controllers nach Init
* Nach C_START k攏nen Objekte empfangen und gesendet werden.
* IM = 0
* RES = 0
* interrupt_mask.enable_receive_interrupt = 1
* interrupt_mask.enable_buss_off_interrupt = 1
* interrupt_mask.enable_error_passive_interrupt = 1
*
*---------------------------------------------------------------------*
* Parameter:
*
* --
*
*---------------------------------------------------------------------*/
void c_start (void)
{
mod_status_type loc_mod_status;
loc_mod_status.auto_decrement_enable = 0;
/* zur乧ksetze IM und RES bit(cpu hat keine Schreibrecht auf BL1,Bl2,OC,BRP Reg.) */
/* Controler auf normal Mode */
loc_mod_status.init_mode = 0;
loc_mod_status.reset_request = 0;
fcan_reg.r.mod_status=loc_mod_status;
can_enable_interrupts();
}
/*---------------------------------------------------------------------*
* C _ S T O P
*---------------------------------------------------------------------*
* Funktion:
* Tempor剅es Anhalten des CAN-Controllers. Es kann mit C_START
* weitergefahren werden. Solange C_STOP aktiv ist, k攏nen keine
* Objekte empfangen oder gesendet werden.
*
* warte
* interrupt_mask.enable_receive_interrupt = 0
* interrupt_mask.enable_buss_off_interrupt = 0
* interrupt_mask.enable_error_passive_interrupt = 0
* Setzt den CAN-Controller in den Hard-Reset-Zustand
* IM = 1
* RES = 1
* RR1,RR2, TRS1,TRS2, RRP1,RRP2 sind zur乧kgesetzt
*
*---------------------------------------------------------------------*
* Parameter:
* --
*
*---------------------------------------------------------------------*/
void c_stop (void)
{
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