shiftlne.vhd

VHDL源代码下载

--shiftlne.vhd n-bitright-to-left shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftlne is
generic ( n : integer := 7 ) ;
port(	
  r	: in std_logic_vector(n-1 downto 0) ;--register input
  l	: in std_logic ;--load
  e	: in std_logic ;--enable
  w	: in std_logic ;--series input
  clock	: in std_logic ;--clock
  q	: buffer std_logic_vector(n-1 downto 0) ) ;--register output
end shiftlne ;
architecture behavior of shiftlne is
begin
  process
  begin
	wait until clock'event and clock = '1' ;
	if e = '1' then
      if l = '1' then
		q <= r ;--parallel load
	  else
	    q(0) <= w ;--series input to lowest bit
	    genbits: for i in 1 to n-1 loop
		  q(i) <= q(i-1) ;--shift low bit to high bit
	    end loop ;
	  end if ;
	end if ;
  end process ;
end behavior ;