scan_1dig.vhd

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library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_arith.all;
   use IEEE.std_logic_unsigned.all;
 
library work;
   use work.my_package.all;

entity SCAN_1DIG is
      Port (RESET : In STD_LOGIC;
	    CLK_10M : In STD_LOGIC;	-- 10MHz Clock
	    TEST : In STD_LOGIC; 
	    SCAN_CODE :	Out STD_LOGIC_VECTOR (7 downto 0);
	    SCAN_ROW : Out STD_LOGIC_VECTOR (7 downto 0));
end SCAN_1DIG;

architecture BEHAVIORAL of SCAN_1DIG is
signal CLK_1M, CLK_1Hz : STD_LOGIC;
signal div10 : STD_LOGIC_VECTOR(3 downto 0);
signal div_1M : STD_LOGIC_VECTOR(19 downto 0);
signal SCAN_LINE : STD_LOGIC_VECTOR(7 downto 0);
signal SCAN_COUNT : STD_LOGIC_VECTOR(2 downto 0);
signal iDISP_CODE : STD_LOGIC_VECTOR(7 downto 0);
signal iFONT_CODE : STD_LOGIC_VECTOR(7 downto 0);
signal iSCAN_ADDR : STD_LOGIC_VECTOR(10 downto 0);

component CHAR_FONT 
Port (SCAN_ADDR : In	STD_LOGIC_VECTOR (10 downto 0);
      FONT_CODE : Out	STD_LOGIC_VECTOR (7 downto 0)
      );
end component;


begin

----------- Clock generator module ------------------------
Clock_generator: block begin
  process(RESET,CLK_10M)
  begin
  	if RESET = '1' then
  		div10 <= "0000";
  		CLK_1M <= '0';	-- 1MHz clock for scan controller
  	elsif CLK_10M'event and CLK_10M = '1' then
  		if div10 = 9 then
  			div10 <= "0000";
  		else
  			div10 <= div10 + 1;
  		end if;
  		if div10 = 4 then
  			CLK_1M <= not CLK_1M;
  		end if;
  	end if;
  end process;

  process(RESET,CLK_1M)
  begin
  	if RESET = '1' then
  		div_1M <= X"00000";
  		CLK_1Hz <= '0';	-- ~1Hz clock
  	elsif CLK_1M'event and CLK_1M = '1' then
		if TEST = '0' then -- Normal use, 
	  		if div_1M(19) = '1' then
  				div_1M <= "00000000000000000000";
  				CLK_1Hz <= not CLK_1Hz;
	  		else
  				div_1M <= div_1M + 1;
	  		end if;
		else -- Test Mode, CLK_1Hz = 1M/16 
	  		if div_1M(3) = '1' then
  				div_1M <= "00000000000000000000";
  				CLK_1Hz <= not CLK_1Hz;
	  		else
  				div_1M <= div_1M + 1;
	  		end if;
  		end if;
  	end if;
  end process;
end block;


----------- 4 bit Hexdecimal counter module ------------------------
Hex_counter: block begin
  process(RESET,CLK_1Hz)
  begin
  	if RESET = '1' then
  		iDISP_CODE <= "00000000";
  	elsif CLK_1Hz'event and CLK_1Hz = '1' then
  		iDISP_CODE <= iDISP_CODE + 1;
  	end if;
  end process;
end block;


----------- 1 digit scan  module ------------------------
scan_module: block begin
  process(RESET,CLK_1M)
  begin
  	if RESET = '1' then
		SCAN_LINE <= "10000000";
		SCAN_COUNT <= "111";  -- Digit Count & Line Count
  	elsif CLK_1M'event and CLK_1M = '1' then
		SCAN_LINE <= SCAN_LINE(6 downto 0) & SCAN_LINE(7); -- rotate left 1 bit
		SCAN_COUNT <= SCAN_COUNT + 1;
  	end if;
  end process;

  iSCAN_ADDR <= iDISP_CODE & SCAN_COUNT(2 downto 0);
  SCAN_CODE <= iFONT_CODE;
  SCAN_ROW <= SCAN_LINE;

  FONT_ROM: CHAR_FONT 
  	Port Map (   
		SCAN_ADDR => iSCAN_ADDR,
		FONT_CODE => iFONT_CODE );

end block;



end BEHAVIORAL;