setp_motor.vhd

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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity step_motor is
port (reset:in STD_LOGIC; --system reset signal
      dir: in STD_LOGIC; --direction
      clk: in STD_LOGIC; --system clock signal
      ini: in STD_LOGIC; --enable switch of loading initial 
      manner: in STD_LOGIC_VECTOR (1 downto 0); --phase excite manner
      angle: in INTEGER range 255 downto 0; --phase define
      baBA: out STD_LOGIC_VECTOR (3 downto 0)); --state output of setp motor
end step_motor;

--define the signal_structure and flow of the device
architecture stepmotor_arch of step_motor is
signal count: INTEGER range 0 to 7; --counter 
signal cntInc: INTEGER range -2 to 2; --count increment
signal cntIni: INTEGER range -1 to 0; --count increment initial
signal angleDnCount: INTEGER range 255 downto 0;  --count how many step-angles processed
signal angleDnCntDec: INTEGER range 2 downto 1;  --angleCount decrement
begin
  -- <<enter your statements here>>

  process(dir, manner, angle)--, ini)
  begin
      --if ini='1' then
      if dir='0' then	
          case manner is
              when "01" => -- 1-