traffic.vhd

VHDL源代码下载

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.traffic_lib.all;
entity traffic is
  port(reset:in std_logic;
       clk:in std_logic;
       a_m:in std_logic;
       st_butt:in std_logic;
       recount:out std_logic;
       next_state:out std_logic;
       sign_state:out std_logic_vector(1 downto 0);
       red:out std_logic_vector(1 downto 0);
       green:out std_logic_vector(1 downto 0);
       yellow:out std_logic_vector(1 downto 0);
       seg7:out std_logic_vector(15 downto 0));
end;

architecture behave of traffic is
signal ena_scan_1:std_logic;
signal ena_1Hz_1:std_logic;
signal flash_1Hz_1:std_logic;
signal recount_1:std_logic;
signal next_state_1:std_logic;
signal sign_state_1:std_logic_vector(1 downto 0);
signal load:std_logic_vector(7 downto 0);
begin
	u1:clk_gen
	   port map(reset,clk,ena_scan_1,ena_1Hz_1,flash_1Hz_1);
	u2:traffic_mux
	   port map(reset,clk,ena_scan_1,recount_1,sign_state_1,load);
	u3:count_down
	   port map(reset,clk,ena_1Hz_1,recount_1,load,seg7,next_state_1);
	u4:traffic_fsm
	   port map(reset,clk,ena_scan_1,ena_1Hz_1,flash_1Hz_1,a_m,st_butt,next_state_1,recount_1,sign_state_1,red,green,yellow);
next_state<=next_state_1;	
recount<=recount_1;
sign_state<=sign_state_1;
end behave;