comcoun.vhd

VHDL源代码下载

--comcoun.vhd 7 segment com scan counter
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comcoun is
port(
  clk : in std_logic;--synchronouse clock
  f1k_ena : in std_logic;--scan clock
  comclk : out std_logic_vector(1 downto 0));--output count
end comcoun;
architecture behavior of comcoun is 
  signal q : std_logic_vector(1 downto 0);--internal counted signal
begin 
  fscan:process(clk)
  begin
    if (clk'event and clk='1') then
      if (f1k_ena='1') then
        if q>=3 then
          q<="00";--initial counter
        else
          q<=q+1;--counting
        end if;
      end if;
    end if;
  end process fscan;
  comclk<=q;--output internal count
end behavior;