shiftrne.vhd

VHDL源代码下载

--shiftrne.vhd n-bit left-to-right shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftrne is
generic ( n : integer := 7 ) ;
port ( 	
  r : in std_logic_vector(n-1 downto 0) ;--register input
  l : in std_logic ;--load
  e : in std_logic ;--enable
  w : in std_logic ;--series input
  clock	: in std_logic ;--clock
  q	: buffer std_logic_vector(n-1 downto 0) ) ;--register output
end shiftrne ;
architecture behavior of shiftrne is	
begin
  process
  begin
    wait until clock'event and clock = '1' ;
	  if e = '1' then
		if l = '1' then
		  q <= r ;--parallel load
		else
		  genbits: for i in 0 to n-2 loop
		    q(i) <= q(i+1) ;--shift high bit to low bit 
	      end loop ;
		  q(n-1) <= w ;--series input to highest bit
		end if ;
	  end if ;
  end process ;
end behavior ;
 ;