my_package.vhd
来自「VHDL源代码下载」· VHDL 代码 · 共 26 行
VHD
26 行
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
package my_package is
type BYTE is array (7 downto 0) of STD_LOGIC;
type RAM_TYPE is array (integer range <>) of UNSIGNED(7 downto 0);
type ROM_TYPE is array (integer range <>) of UNSIGNED(7 downto 0);
end my_package;
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package body my_package is
end my_package;
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