scan_gen.vhd

VHDL源代码下载

-scan_gen.vhd keyboard scan_clock generator
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scan_gen is
generic (osc_f : integer := 3686 ; osc_bit : integer := 12);
--generic (osc_f : integer := 100 ; osc_bit : integer := 7); for testing
port(
  clk : in std_logic;--clock
  scan_f : out std_logic);--1khz
end scan_gen;
architecture behavior of scan_gen is 
begin 
  scan_freq:process(clk)
    variable qscan : std_logic_vector(osc_bit-1 downto 0);
  begin
    if(clk'event and clk='1')then
      if (qscan>=osc_f-1) then
        for i in osc_bit-1 downto 0 loop
          qscan(i):='0';--reset to zero
        end loop;
      else
        qscan:=qscan+1;
      end if;
    end if;
    if (qscan>=osc_f-1) then
      scan_f<='1';--count to osc_f then generate pulse
    else
      scan_f<='0';--remain zero
    end if;
  end process scan_freq;
end behavior;