📄 irq.lst
字号:
*** CODE SEGMENT '?PR?IRQ_Handler?A?irq':
11: void IRQ_Handler(void) __irq {
00000000 E92D5F0F STMDB R13!,{R0-R3,R8-R12,LR}
20: if((IRQSTA & GP_TIMER_BIT)) // Timer1 IRQ?
00000004 E5100000 LDR R0,=0xFFFF0000
00000008 E5900000 LDR R0,[R0,#0x0]
0000000C E3100008 TST R0,#0x0008
00000010 0A000041 BEQ L_1 ; Targ=0x11C
23: T1CON = 0x00;
00000014 E3A01000 MOV R1,#0x0
00000018 E5100000 LDR R0,=0xFFFF0328
0000001C E5801000 STR R1,[R0,#0x0]
25: if((i2c_receive != 0x00) && (i2c_first == TRUE)) {
00000020 E5100000 LDR R0,=i2c_receive ; i2c_receive
00000024 E5D00000 LDRB R0,[R0,#0x0] ; i2c_receive
00000028 E3500000 CMP R0,#0x0000
0000002C 0A000009 BEQ L_2 ; Targ=0x58
00000030 E5100000 LDR R0,=i2c_first ; i2c_first
00000034 E5D00000 LDRB R0,[R0,#0x0] ; i2c_first
00000038 E3500001 CMP R0,#0x0001
0000003C 1A000005 BNE L_2 ; Targ=0x58
26: FlashUpdate(i2c_receive);
00000040 E5100000 LDR R0,=i2c_receive ; i2c_receive
00000044 E5D00000 LDRB R0,[R0,#0x0] ; i2c_receive
00000048 EBFFFFEC BL FlashUpdate?A ; Targ=0x0
27: i2c_receive = 0x00;
0000004C E3A01000 MOV R1,#0x0
00000050 E5100000 LDR R0,=i2c_receive ; i2c_receive
00000054 E5C01000 STRB R1,[R0,#0x0] ; i2c_receive
28: }
00000058 L_2:
31: if(dac_update == 0x01) SetDac(0);
00000058 E5100000 LDR R0,=dac_update ; dac_update
0000005C E5D00000 LDRB R0,[R0,#0x0] ; dac_update
ARM COMPILER V2.32a, irq 08/08/05 09:50:23 PAGE 4
00000060 E3500001 CMP R0,#0x0001
00000064 1A000001 BNE L_3 ; Targ=0x70
00000068 E3A00000 MOV R0,#0x0
0000006C EBFFFFE3 BL SetDac?A ; Targ=0x0
00000070 L_3:
32: if(dac_update == 0x02) SetDac(1);
00000070 E5100000 LDR R0,=dac_update ; dac_update
00000074 E5D00000 LDRB R0,[R0,#0x0] ; dac_update
00000078 E3500002 CMP R0,#0x0002
0000007C 1A000001 BNE L_4 ; Targ=0x88
00000080 E3A00001 MOV R0,#0x1
00000084 EBFFFFDD BL SetDac?A ; Targ=0x0
00000088 L_4:
34: monitor(); // run monitor routines
00000088 EBFFFFDC BL monitor?A ; Targ=0x0
35: diag(); // run diagnostic routnies
0000008C EBFFFFDB BL diag?A ; Targ=0x0
36: fault_recovery_check(); // check recovery status
00000090 EBFFFFDA BL fault_recovery_check?A ; Targ=0x0
38: if(ER_CON)ErCalibration(ER_CON); // run ER caliburation
00000094 E5100000 LDR R0,=A2h + 0x90 ; A2h+144
00000098 E5D00000 LDRB R0,[R0,#0x0] ; A2h+144
0000009C E3500000 CMP R0,#0x0000
000000A0 0A000002 BEQ L_5 ; Targ=0xB0
000000A4 E5100000 LDR R0,=A2h + 0x90 ; A2h+144
000000A8 E5D00000 LDRB R0,[R0,#0x0] ; A2h+144
000000AC EBFFFFD3 BL ErCalibration?A ; Targ=0x0
000000B0 L_5:
39: if((er_count>=ER_COMP_TIME) && ER_COMP_ENABLE){
000000B0 E5100000 LDR R0,=er_count ; er_count
000000B4 E1D000B0 LDRH R0,[R0,#0x0] ; er_count
000000B8 E350000A CMP R0,#0x000A
000000BC 3A000007 BCC L_6 ; Targ=0xE0
000000C0 E5100000 LDR R0,=A2h + 0x91 ; A2h+145
000000C4 E5D00000 LDRB R0,[R0,#0x0] ; A2h+145
000000C8 E3500000 CMP R0,#0x0000
000000CC 0A000003 BEQ L_6 ; Targ=0xE0
40: ErCompensation(); // run ER compensation
000000D0 EBFFFFCA BL ErCompensation?A ; Targ=0x0
41: er_count=0; // reset counter
000000D4 E3A01000 MOV R1,#0x0
000000D8 E5100000 LDR R0,=er_count ; er_count
000000DC E1C010B0 STRH R1,[R0,#0x0] ; er_count
42: }
000000E0 L_6:
44: A2h[110] &= 0xFE; // clear bit0, DATA_READY_BAR in Status/Control Bits
000000E0 E5100000 LDR R0,=A2h + 0x6E ; A2h+110
000000E4 E5D01000 LDRB R1,[R0,#0x0] ; A2h+110
000000E8 E20110FE AND R1,R1,#0x00FE
000000EC E5100000 LDR R0,=A2h + 0x6E ; A2h+110
000000F0 E5C01000 STRB R1,[R0,#0x0] ; A2h+110
45: er_count++;
000000F4 E5100000 LDR R0,=er_count ; er_count
000000F8 E1D010B0 LDRH R1,[R0,#0x0] ; er_count
000000FC E2811001 ADD R1,R1,#0x0001
00000100 E1C010B0 STRH R1,[R0,#0x0] ; er_count
47: T1CLRI = 0; // clear Timer1 interrupt
00000104 E3A01000 MOV R1,#0x0
00000108 E5100000 LDR R0,=0xFFFF032C
0000010C E5801000 STR R1,[R0,#0x0]
48: T1CON = 0xCF;
00000110 E3A010CF MOV R1,#0xCF
00000114 E5100000 LDR R0,=0xFFFF0328
00000118 E5801000 STR R1,[R0,#0x0]
49: }
0000011C L_1:
ARM COMPILER V2.32a, irq 08/08/05 09:50:23 PAGE 5
57: if ((IRQSTA & XIRQ0_BIT) == 0x00008000) // XIRQ0, bit15
0000011C E5100000 LDR R0,=0xFFFF0000
00000120 E5900000 LDR R0,[R0,#0x0]
00000124 E3100902 TST R0,#0x8000
00000128 0A000007 BEQ L_7 ; Targ=0x14C
60: A2h[110] |= 0x04; // bit2(Tx Fault state) is set high
0000012C E5100000 LDR R0,=A2h + 0x6E ; A2h+110
00000130 E5D01000 LDRB R1,[R0,#0x0] ; A2h+110
00000134 E3811004 ORR R1,R1,#0x0004
00000138 E5100000 LDR R0,=A2h + 0x6E ; A2h+110
0000013C E5C01000 STRB R1,[R0,#0x0] ; A2h+110
62: IRQCLR = 0x00008000; // disable XIRQ0 interrupt
00000140 E3A01902 MOV R1,#0x8000
00000144 E5100000 LDR R0,=0xFFFF000C
00000148 E5801000 STR R1,[R0,#0x0]
63: }
0000014C L_7:
70: if ((IRQSTA & XIRQ1_BIT) == 0x00040000) // XIRQ1, bit14
0000014C E5100000 LDR R0,=0xFFFF0000
00000150 E5900000 LDR R0,[R0,#0x0]
00000154 E3100701 TST R0,#0x40000
00000158 0A000007 BEQ L_8 ; Targ=0x17C
73: A2h[110] |= 0x80; // bit7(Tx Disable state) is set high
0000015C E5100000 LDR R0,=A2h + 0x6E ; A2h+110
00000160 E5D01000 LDRB R1,[R0,#0x0] ; A2h+110
00000164 E3811080 ORR R1,R1,#0x0080
00000168 E5100000 LDR R0,=A2h + 0x6E ; A2h+110
0000016C E5C01000 STRB R1,[R0,#0x0] ; A2h+110
75: IRQCLR = 0x00040000; // disable XIRQ1 interrupt
00000170 E3A01701 MOV R1,#0x40000
00000174 E5100000 LDR R0,=0xFFFF000C
00000178 E5801000 STR R1,[R0,#0x0]
76: }
0000017C L_8:
109: }
0000017C E8BD5F0F LDMIA R13!,{R0-R3,R8-R12,LR}
00000180 E25EF004 SUBS R15,R14,#0x0004
00000184 ENDP ; 'IRQ_Handler?A'
Module Information Static
----------------------------------
code size = ------
data size = 2
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -