📄 diag.lst
字号:
00000200 20BF MOV R0,#0xBF
00000202 4001 AND R1,R0
00000204 4800 LDR R0,=A2h + 0x70 ; A2h+112
00000206 7001 STRB R1,[R0,#0x0] ; A2h+112
66: break;
00000208 E016 B L_9 ; T=0x00000238
67: case 1:
0000020A L_10:
68: A2h[112] &= 0x7F; // clear high alarm flag bit7
0000020A 4800 LDR R0,=A2h + 0x70 ; A2h+112
0000020C 7801 LDRB R1,[R0,#0x0] ; A2h+112
0000020E 207F MOV R0,#0x7F
00000210 4001 AND R1,R0
00000212 4800 LDR R0,=A2h + 0x70 ; A2h+112
00000214 7001 STRB R1,[R0,#0x0] ; A2h+112
69: A2h[116] &= 0x7F; // clear high warning flag bit7
00000216 4800 LDR R0,=A2h + 0x74 ; A2h+116
00000218 7801 LDRB R1,[R0,#0x0] ; A2h+116
0000021A 207F MOV R0,#0x7F
0000021C 4001 AND R1,R0
0000021E 4800 LDR R0,=A2h + 0x74 ; A2h+116
00000220 7001 STRB R1,[R0,#0x0] ; A2h+116
70: A2h[116] |= 0x40; // set low warning flag bit6
00000222 4800 LDR R0,=A2h + 0x74 ; A2h+116
00000224 7801 LDRB R1,[R0,#0x0] ; A2h+116
00000226 2040 MOV R0,#0x40
00000228 4301 ORR R1,R0
0000022A 4800 LDR R0,=A2h + 0x74 ; A2h+116
0000022C 7001 STRB R1,[R0,#0x0] ; A2h+116
ARM COMPILER V2.32a, diag 08/08/05 09:50:22 PAGE 13
71: A2h[112] |= 0x40; // set low alarm flag bit6
0000022E 4800 LDR R0,=A2h + 0x70 ; A2h+112
00000230 7801 LDRB R1,[R0,#0x0] ; A2h+112
00000232 2040 MOV R0,#0x40
00000234 4301 ORR R1,R0
00000236 4800 LDR R0,=A2h + 0x70 ; A2h+112
00000238 7001 STRB R1,[R0,#0x0] ; A2h+112
73: }
0000023A L_9:
0000023A ; SCOPE-END
74: }
0000023A B006 ADD R13,#0x18
0000023C B003 ADD R13,#0xC
0000023E 4770 BX R14
00000240 ENDP ; 'temp_diag?T'
*** CODE SEGMENT '?PR?voltage_diag?T?diag':
81: void voltage_diag(BYTE msb, BYTE lsb, BYTE addr){
00000000 B407 PUSH {R0-R2}
00000002 B086 SUB R13,#0x18
00000004 ; SCOPE-START
84: HALFWORD monitor = (msb<<8) + lsb;
00000004 A806 ADD R0,R13,#0x18
00000006 7800 LDRB R0,[R0,#0x0] ; msb
00000008 1C01 MOV R1,R0
0000000A 0209 LSL R1,R1,#0x8
0000000C A807 ADD R0,R13,#0x1C
0000000E 7800 LDRB R0,[R0,#0x0] ; lsb
00000010 1809 ADD R1,R0
00000012 A801 ADD R0,R13,#0x4
00000014 8001 STRH R1,[R0,#0x0] ; monitor
85: HALFWORD high_alarm = (A2h[addr ]<<8) + A2h[addr+1];
00000016 A808 ADD R0,R13,#0x20
00000018 7800 LDRB R0,[R0,#0x0] ; addr
0000001A 1C01 MOV R1,R0
0000001C 4800 LDR R0,=A2h ; A2h
0000001E 1840 ADD R0,R1 ; A2h
00000020 7800 LDRB R0,[R0,#0x0]
00000022 1C01 MOV R1,R0
00000024 0209 LSL R1,R1,#0x8
00000026 A808 ADD R0,R13,#0x20
00000028 7800 LDRB R0,[R0,#0x0] ; addr
0000002A 1C02 MOV R2,R0
0000002C 4800 LDR R0,=A2h + 0x1 ; A2h+1
0000002E 1880 ADD R0,R2 ; A2h+1
00000030 7800 LDRB R0,[R0,#0x0]
00000032 1809 ADD R1,R0
00000034 A802 ADD R0,R13,#0x8
00000036 8001 STRH R1,[R0,#0x0] ; high_alarm
86: HALFWORD low_alarm = (A2h[addr+2]<<8) + A2h[addr+3];
00000038 A808 ADD R0,R13,#0x20
0000003A 7800 LDRB R0,[R0,#0x0] ; addr
0000003C 1C01 MOV R1,R0
0000003E 4800 LDR R0,=A2h + 0x2 ; A2h+2
00000040 1840 ADD R0,R1 ; A2h+2
00000042 7800 LDRB R0,[R0,#0x0]
00000044 1C01 MOV R1,R0
00000046 0209 LSL R1,R1,#0x8
00000048 A808 ADD R0,R13,#0x20
0000004A 7800 LDRB R0,[R0,#0x0] ; addr
0000004C 1C02 MOV R2,R0
0000004E 4800 LDR R0,=A2h + 0x3 ; A2h+3
00000050 1880 ADD R0,R2 ; A2h+3
00000052 7800 LDRB R0,[R0,#0x0]
00000054 1809 ADD R1,R0
00000056 A803 ADD R0,R13,#0xC
00000058 8001 STRH R1,[R0,#0x0] ; low_alarm
ARM COMPILER V2.32a, diag 08/08/05 09:50:22 PAGE 14
87: HALFWORD high_warning = (A2h[addr+4]<<8) + A2h[addr+5];
0000005A A808 ADD R0,R13,#0x20
0000005C 7800 LDRB R0,[R0,#0x0] ; addr
0000005E 1C01 MOV R1,R0
00000060 4800 LDR R0,=A2h + 0x4 ; A2h+4
00000062 1840 ADD R0,R1 ; A2h+4
00000064 7800 LDRB R0,[R0,#0x0]
00000066 1C01 MOV R1,R0
00000068 0209 LSL R1,R1,#0x8
0000006A A808 ADD R0,R13,#0x20
0000006C 7800 LDRB R0,[R0,#0x0] ; addr
0000006E 1C02 MOV R2,R0
00000070 4800 LDR R0,=A2h + 0x5 ; A2h+5
00000072 1880 ADD R0,R2 ; A2h+5
00000074 7800 LDRB R0,[R0,#0x0]
00000076 1809 ADD R1,R0
00000078 A804 ADD R0,R13,#0x10
0000007A 8001 STRH R1,[R0,#0x0] ; high_warning
88: HALFWORD low_warning = (A2h[addr+6]<<8) + A2h[addr+7];
0000007C A808 ADD R0,R13,#0x20
0000007E 7800 LDRB R0,[R0,#0x0] ; addr
00000080 1C01 MOV R1,R0
00000082 4800 LDR R0,=A2h + 0x6 ; A2h+6
00000084 1840 ADD R0,R1 ; A2h+6
00000086 7800 LDRB R0,[R0,#0x0]
00000088 1C01 MOV R1,R0
0000008A 0209 LSL R1,R1,#0x8
0000008C A808 ADD R0,R13,#0x20
0000008E 7800 LDRB R0,[R0,#0x0] ; addr
00000090 1C02 MOV R2,R0
00000092 4800 LDR R0,=A2h + 0x7 ; A2h+7
00000094 1880 ADD R0,R2 ; A2h+7
00000096 7800 LDRB R0,[R0,#0x0]
00000098 1809 ADD R1,R0
0000009A A805 ADD R0,R13,#0x14
0000009C 8001 STRH R1,[R0,#0x0] ; low_warning
90: if (monitor>high_alarm) result=5;
0000009E A802 ADD R0,R13,#0x8
000000A0 8800 LDRH R0,[R0,#0x0] ; high_alarm
000000A2 1C01 MOV R1,R0
000000A4 A801 ADD R0,R13,#0x4
000000A6 8800 LDRH R0,[R0,#0x0] ; monitor
000000A8 4288 CMP R0,R1
000000AA D903 BLS L_15 ; T=0x000000B4
000000AC 2105 MOV R1,#0x5
000000AE A800 ADD R0,R13,#0x0
000000B0 7001 STRB R1,[R0,#0x0] ; result
000000B2 E038 B L_16 ; T=0x00000126
000000B4 L_15:
91: else if (monitor>high_warning && monitor<=high_alarm) result=4;
000000B4 A804 ADD R0,R13,#0x10
000000B6 8800 LDRH R0,[R0,#0x0] ; high_warning
000000B8 1C01 MOV R1,R0
000000BA A801 ADD R0,R13,#0x4
000000BC 8800 LDRH R0,[R0,#0x0] ; monitor
000000BE 4288 CMP R0,R1
000000C0 D90A BLS L_17 ; T=0x000000D8
000000C2 A802 ADD R0,R13,#0x8
000000C4 8800 LDRH R0,[R0,#0x0] ; high_alarm
000000C6 1C01 MOV R1,R0
000000C8 A801 ADD R0,R13,#0x4
000000CA 8800 LDRH R0,[R0,#0x0] ; monitor
000000CC 4288 CMP R0,R1
000000CE D803 BHI L_17 ; T=0x000000D8
000000D0 2104 MOV R1,#0x4
000000D2 A800 ADD R0,R13,#0x0
ARM COMPILER V2.32a, diag 08/08/05 09:50:22 PAGE 15
000000D4 7001 STRB R1,[R0,#0x0] ; result
000000D6 E026 B L_16 ; T=0x00000126
000000D8 L_17:
92: else if (monitor<=high_warning && monitor>=low_warning) result=3;
000000D8 A804 ADD R0,R13,#0x10
000000DA 8800 LDRH R0,[R0,#0x0] ; high_warning
000000DC 1C01 MOV R1,R0
000000DE A801 ADD R0,R13,#0x4
000000E0 8800 LDRH R0,[R0,#0x0] ; monitor
000000E2 4288 CMP R0,R1
000000E4 D80A BHI L_19 ; T=0x000000FC
000000E6 A805 ADD R0,R13,#0x14
000000E8 8800 LDRH R0,[R0,#0x0] ; low_warning
000000EA 1C01 MOV R1,R0
000000EC A801 ADD R0,R13,#0x4
000000EE 8800 LDRH R0,[R0,#0x0] ; monitor
000000F0 4288 CMP R0,R1
000000F2 D303 BCC L_19 ; T=0x000000FC
000000F4 2103 MOV R1,#0x3
000000F6 A800 ADD R0,R13,#0x0
000000F8 7001 STRB R1,[R0,#0x0] ; result
000000FA E014 B L_16 ; T=0x00000126
000000FC L_19:
93: else if (monitor<low_warning && monitor>= low_alarm) result=2;
000000FC A805 ADD R0,R13,#0x14
000000FE 8800 LDRH R0,[R0,#0x0] ; low_warning
00000100 1C01 MOV R1,R0
00000102 A801 ADD R0,R13,#0x4
00000104 8800 LDRH R0,[R0,#0x0] ; monitor
00000106 4288 CMP R0,R1
00000108 D20A BCS L_21 ; T=0x00000120
0000010A A803 ADD R0,R13,#0xC
0000010C 8800 LDRH R0,[R0,#0x0] ; low_alarm
0000010E 1C01 MOV R1,R0
00000110 A801 ADD R0,R13,#0x4
00000112 8800 LDRH R0,[R0,#0x0] ; monitor
00000114 4288 CMP R0,R1
00000116 D303 BCC L_21 ; T=0x00000120
00000118 2102 MOV R1,#0x2
0000011A A800 ADD R0,R13,#0x0
0000011C 7001 STRB R1,[R0,#0x0] ; result
0000011E E002 B L_16 ; T=0x00000126
00000120 L_21:
94: else result=1;
00000120 2101 MOV R1,#0x1
00000122 A800 ADD R0,R13,#0x0
00000124 7001 STRB R1,[R0,#0x0] ; result
00000126 L_16:
96: switch (result)
00000126 A800 ADD R0,R13,#0x0
00000128 7800 LDRB R0,[R0,#0x0] ; result
0000012A 2801 CMP R0,#0x1
0000012C D06C BEQ L_24 ; T=0x00000208
0000012E 2802 CMP R0,#0x2
00000130 D051 BEQ L_25 ; T=0x000001D6
00000132 2803 CMP R0,#0x3
00000134 D036 BEQ L_26 ; T=0x000001A4
00000136 2804 CMP R0,#0x4
00000138 D01B BEQ L_27 ; T=0x00000172
0000013A 2805 CMP R0,#0x5
0000013C D000 BNE $+4
0000013E E07B B L_23 ; T=0x00000238
98: case 5:
00000142 L_28:
99: A2h[112] |= 0x20; // set high alarm flag bit5
00000142 4800 LDR R0,=A2h + 0x70 ; A2h+112
ARM COMPILER V2.32a, diag 08/08/05 09:50:22 PAGE 16
00000144 7801 LDRB R1,[R0,#0x0] ; A2h+112
00000146 2020 MOV R0,#0x20
00000148 4301 ORR R1,R0
0000014A 4800 LDR R0,=A2h + 0x70 ; A2h+112
0000014C 7001 STRB R1,[R0,#0x0] ; A2h+112
100: A2h[116] |= 0x20; // set high warning flag bit5
0000014E 4800 LDR R0,=A2h + 0x74 ; A2h+116
00000150 7801 LDRB R1,[R0,#0x0] ; A2h+116
00000152 2020 MOV R0,#0x20
00000154 4301 ORR R1,R0
00000156 4800 LDR R0,=A2h + 0x74 ; A2h+116
00000158 7001 STRB R1,[R0,#0x0] ; A2h+116
101: A2h[116] &= 0xEF; // clear low warning flag bit4
0000015A 4800 LDR R0,=A2h + 0x74 ; A2h+116
0000015C 7801 LDRB R1,[R0,#0x0] ; A2h+116
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