📄 diag.lst
字号:
00000064 7800 LDRB R0,[R0,#0x0]
00000066 1C01 MOV R1,R0
00000068 0209 LSL R1,R1,#0x8
0000006A A808 ADD R0,R13,#0x20
0000006C 7800 LDRB R0,[R0,#0x0] ; addr
0000006E 1C02 MOV R2,R0
00000070 4800 LDR R0,=A2h + 0x5 ; A2h+5
00000072 1880 ADD R0,R2 ; A2h+5
00000074 7800 LDRB R0,[R0,#0x0]
ARM COMPILER V2.32a, diag 08/08/05 09:50:22 PAGE 9
00000076 1809 ADD R1,R0
00000078 A804 ADD R0,R13,#0x10
0000007A 8001 STRH R1,[R0,#0x0] ; high_warning
33: HALFWORD low_warning = (A2h[addr+6]<<8) + A2h[addr+7];
0000007C A808 ADD R0,R13,#0x20
0000007E 7800 LDRB R0,[R0,#0x0] ; addr
00000080 1C01 MOV R1,R0
00000082 4800 LDR R0,=A2h + 0x6 ; A2h+6
00000084 1840 ADD R0,R1 ; A2h+6
00000086 7800 LDRB R0,[R0,#0x0]
00000088 1C01 MOV R1,R0
0000008A 0209 LSL R1,R1,#0x8
0000008C A808 ADD R0,R13,#0x20
0000008E 7800 LDRB R0,[R0,#0x0] ; addr
00000090 1C02 MOV R2,R0
00000092 4800 LDR R0,=A2h + 0x7 ; A2h+7
00000094 1880 ADD R0,R2 ; A2h+7
00000096 7800 LDRB R0,[R0,#0x0]
00000098 1809 ADD R1,R0
0000009A A805 ADD R0,R13,#0x14
0000009C 8001 STRH R1,[R0,#0x0] ; low_warning
35: if (monitor>high_alarm) result=5;
0000009E A802 ADD R0,R13,#0x8
000000A0 8800 LDRH R0,[R0,#0x0] ; high_alarm
000000A2 1C01 MOV R1,R0
000000A4 A801 ADD R0,R13,#0x4
000000A6 8800 LDRH R0,[R0,#0x0] ; monitor
000000A8 4288 CMP R0,R1
000000AA D903 BLS L_1 ; T=0x000000B4
000000AC 2105 MOV R1,#0x5
000000AE A800 ADD R0,R13,#0x0
000000B0 7001 STRB R1,[R0,#0x0] ; result
000000B2 E038 B L_2 ; T=0x00000126
000000B4 L_1:
36: else if (monitor>high_warning && monitor<=high_alarm) result=4;
000000B4 A804 ADD R0,R13,#0x10
000000B6 8800 LDRH R0,[R0,#0x0] ; high_warning
000000B8 1C01 MOV R1,R0
000000BA A801 ADD R0,R13,#0x4
000000BC 8800 LDRH R0,[R0,#0x0] ; monitor
000000BE 4288 CMP R0,R1
000000C0 D90A BLS L_3 ; T=0x000000D8
000000C2 A802 ADD R0,R13,#0x8
000000C4 8800 LDRH R0,[R0,#0x0] ; high_alarm
000000C6 1C01 MOV R1,R0
000000C8 A801 ADD R0,R13,#0x4
000000CA 8800 LDRH R0,[R0,#0x0] ; monitor
000000CC 4288 CMP R0,R1
000000CE D803 BHI L_3 ; T=0x000000D8
000000D0 2104 MOV R1,#0x4
000000D2 A800 ADD R0,R13,#0x0
000000D4 7001 STRB R1,[R0,#0x0] ; result
000000D6 E026 B L_2 ; T=0x00000126
000000D8 L_3:
37: else if (monitor<=high_warning && monitor>=low_warning) result=3;
000000D8 A804 ADD R0,R13,#0x10
000000DA 8800 LDRH R0,[R0,#0x0] ; high_warning
000000DC 1C01 MOV R1,R0
000000DE A801 ADD R0,R13,#0x4
000000E0 8800 LDRH R0,[R0,#0x0] ; monitor
000000E2 4288 CMP R0,R1
000000E4 D80A BHI L_5 ; T=0x000000FC
000000E6 A805 ADD R0,R13,#0x14
000000E8 8800 LDRH R0,[R0,#0x0] ; low_warning
000000EA 1C01 MOV R1,R0
000000EC A801 ADD R0,R13,#0x4
ARM COMPILER V2.32a, diag 08/08/05 09:50:22 PAGE 10
000000EE 8800 LDRH R0,[R0,#0x0] ; monitor
000000F0 4288 CMP R0,R1
000000F2 D303 BCC L_5 ; T=0x000000FC
000000F4 2103 MOV R1,#0x3
000000F6 A800 ADD R0,R13,#0x0
000000F8 7001 STRB R1,[R0,#0x0] ; result
000000FA E014 B L_2 ; T=0x00000126
000000FC L_5:
38: else if (monitor<low_warning && monitor>= low_alarm) result=2;
000000FC A805 ADD R0,R13,#0x14
000000FE 8800 LDRH R0,[R0,#0x0] ; low_warning
00000100 1C01 MOV R1,R0
00000102 A801 ADD R0,R13,#0x4
00000104 8800 LDRH R0,[R0,#0x0] ; monitor
00000106 4288 CMP R0,R1
00000108 D20A BCS L_7 ; T=0x00000120
0000010A A803 ADD R0,R13,#0xC
0000010C 8800 LDRH R0,[R0,#0x0] ; low_alarm
0000010E 1C01 MOV R1,R0
00000110 A801 ADD R0,R13,#0x4
00000112 8800 LDRH R0,[R0,#0x0] ; monitor
00000114 4288 CMP R0,R1
00000116 D303 BCC L_7 ; T=0x00000120
00000118 2102 MOV R1,#0x2
0000011A A800 ADD R0,R13,#0x0
0000011C 7001 STRB R1,[R0,#0x0] ; result
0000011E E002 B L_2 ; T=0x00000126
00000120 L_7:
39: else result=1;
00000120 2101 MOV R1,#0x1
00000122 A800 ADD R0,R13,#0x0
00000124 7001 STRB R1,[R0,#0x0] ; result
00000126 L_2:
41: switch (result)
00000126 A800 ADD R0,R13,#0x0
00000128 7800 LDRB R0,[R0,#0x0] ; result
0000012A 2801 CMP R0,#0x1
0000012C D06C BEQ L_10 ; T=0x00000208
0000012E 2802 CMP R0,#0x2
00000130 D051 BEQ L_11 ; T=0x000001D6
00000132 2803 CMP R0,#0x3
00000134 D036 BEQ L_12 ; T=0x000001A4
00000136 2804 CMP R0,#0x4
00000138 D01B BEQ L_13 ; T=0x00000172
0000013A 2805 CMP R0,#0x5
0000013C D000 BNE $+4
0000013E E07B B L_9 ; T=0x00000238
43: case 5:
00000142 L_14:
44: A2h[112] |= 0x80; // set high alarm flag bit7
00000142 4800 LDR R0,=A2h + 0x70 ; A2h+112
00000144 7801 LDRB R1,[R0,#0x0] ; A2h+112
00000146 2080 MOV R0,#0x80
00000148 4301 ORR R1,R0
0000014A 4800 LDR R0,=A2h + 0x70 ; A2h+112
0000014C 7001 STRB R1,[R0,#0x0] ; A2h+112
45: A2h[116] |= 0x80; // set high warning flag bit7
0000014E 4800 LDR R0,=A2h + 0x74 ; A2h+116
00000150 7801 LDRB R1,[R0,#0x0] ; A2h+116
00000152 2080 MOV R0,#0x80
00000154 4301 ORR R1,R0
00000156 4800 LDR R0,=A2h + 0x74 ; A2h+116
00000158 7001 STRB R1,[R0,#0x0] ; A2h+116
46: A2h[116] &= 0xBF; // clear low warning flag bit6
0000015A 4800 LDR R0,=A2h + 0x74 ; A2h+116
0000015C 7801 LDRB R1,[R0,#0x0] ; A2h+116
ARM COMPILER V2.32a, diag 08/08/05 09:50:22 PAGE 11
0000015E 20BF MOV R0,#0xBF
00000160 4001 AND R1,R0
00000162 4800 LDR R0,=A2h + 0x74 ; A2h+116
00000164 7001 STRB R1,[R0,#0x0] ; A2h+116
47: A2h[112] &= 0xBF; // clear low alarm flag bit6
00000166 4800 LDR R0,=A2h + 0x70 ; A2h+112
00000168 7801 LDRB R1,[R0,#0x0] ; A2h+112
0000016A 20BF MOV R0,#0xBF
0000016C 4001 AND R1,R0
0000016E 4800 LDR R0,=A2h + 0x70 ; A2h+112
00000170 7001 STRB R1,[R0,#0x0] ; A2h+112
48: break;
00000172 E061 B L_9 ; T=0x00000238
49: case 4:
00000174 L_13:
50: A2h[112] &= 0x7F; // clear high alarm flag bit7
00000174 4800 LDR R0,=A2h + 0x70 ; A2h+112
00000176 7801 LDRB R1,[R0,#0x0] ; A2h+112
00000178 207F MOV R0,#0x7F
0000017A 4001 AND R1,R0
0000017C 4800 LDR R0,=A2h + 0x70 ; A2h+112
0000017E 7001 STRB R1,[R0,#0x0] ; A2h+112
51: A2h[116] |= 0x80; // set high warning flag bit7
00000180 4800 LDR R0,=A2h + 0x74 ; A2h+116
00000182 7801 LDRB R1,[R0,#0x0] ; A2h+116
00000184 2080 MOV R0,#0x80
00000186 4301 ORR R1,R0
00000188 4800 LDR R0,=A2h + 0x74 ; A2h+116
0000018A 7001 STRB R1,[R0,#0x0] ; A2h+116
52: A2h[116] &= 0xBF; // clear low warning flag bit6
0000018C 4800 LDR R0,=A2h + 0x74 ; A2h+116
0000018E 7801 LDRB R1,[R0,#0x0] ; A2h+116
00000190 20BF MOV R0,#0xBF
00000192 4001 AND R1,R0
00000194 4800 LDR R0,=A2h + 0x74 ; A2h+116
00000196 7001 STRB R1,[R0,#0x0] ; A2h+116
53: A2h[112] &= 0xBF; // clear low alarm flag bit6
00000198 4800 LDR R0,=A2h + 0x70 ; A2h+112
0000019A 7801 LDRB R1,[R0,#0x0] ; A2h+112
0000019C 20BF MOV R0,#0xBF
0000019E 4001 AND R1,R0
000001A0 4800 LDR R0,=A2h + 0x70 ; A2h+112
000001A2 7001 STRB R1,[R0,#0x0] ; A2h+112
54: break;
000001A4 E048 B L_9 ; T=0x00000238
55: case 3:
000001A6 L_12:
56: A2h[112] &= 0x7F; // clear high alarm flag bit7
000001A6 4800 LDR R0,=A2h + 0x70 ; A2h+112
000001A8 7801 LDRB R1,[R0,#0x0] ; A2h+112
000001AA 207F MOV R0,#0x7F
000001AC 4001 AND R1,R0
000001AE 4800 LDR R0,=A2h + 0x70 ; A2h+112
000001B0 7001 STRB R1,[R0,#0x0] ; A2h+112
57: A2h[116] &= 0x7F; // clear high warning flag bit7
000001B2 4800 LDR R0,=A2h + 0x74 ; A2h+116
000001B4 7801 LDRB R1,[R0,#0x0] ; A2h+116
000001B6 207F MOV R0,#0x7F
000001B8 4001 AND R1,R0
000001BA 4800 LDR R0,=A2h + 0x74 ; A2h+116
000001BC 7001 STRB R1,[R0,#0x0] ; A2h+116
58: A2h[116] &= 0xBF; // clear low warning flag bit6
000001BE 4800 LDR R0,=A2h + 0x74 ; A2h+116
000001C0 7801 LDRB R1,[R0,#0x0] ; A2h+116
000001C2 20BF MOV R0,#0xBF
000001C4 4001 AND R1,R0
ARM COMPILER V2.32a, diag 08/08/05 09:50:22 PAGE 12
000001C6 4800 LDR R0,=A2h + 0x74 ; A2h+116
000001C8 7001 STRB R1,[R0,#0x0] ; A2h+116
59: A2h[112] &= 0xBF; // clear low alarm flag bit6
000001CA 4800 LDR R0,=A2h + 0x70 ; A2h+112
000001CC 7801 LDRB R1,[R0,#0x0] ; A2h+112
000001CE 20BF MOV R0,#0xBF
000001D0 4001 AND R1,R0
000001D2 4800 LDR R0,=A2h + 0x70 ; A2h+112
000001D4 7001 STRB R1,[R0,#0x0] ; A2h+112
60: break;
000001D6 E02F B L_9 ; T=0x00000238
61: case 2:
000001D8 L_11:
62: A2h[112] &= 0x7F; // clear high alarm flag bit7
000001D8 4800 LDR R0,=A2h + 0x70 ; A2h+112
000001DA 7801 LDRB R1,[R0,#0x0] ; A2h+112
000001DC 207F MOV R0,#0x7F
000001DE 4001 AND R1,R0
000001E0 4800 LDR R0,=A2h + 0x70 ; A2h+112
000001E2 7001 STRB R1,[R0,#0x0] ; A2h+112
63: A2h[116] &= 0x7F; // clear high warning flag bit7
000001E4 4800 LDR R0,=A2h + 0x74 ; A2h+116
000001E6 7801 LDRB R1,[R0,#0x0] ; A2h+116
000001E8 207F MOV R0,#0x7F
000001EA 4001 AND R1,R0
000001EC 4800 LDR R0,=A2h + 0x74 ; A2h+116
000001EE 7001 STRB R1,[R0,#0x0] ; A2h+116
64: A2h[116] |= 0x40; // set low warning flag bit6
000001F0 4800 LDR R0,=A2h + 0x74 ; A2h+116
000001F2 7801 LDRB R1,[R0,#0x0] ; A2h+116
000001F4 2040 MOV R0,#0x40
000001F6 4301 ORR R1,R0
000001F8 4800 LDR R0,=A2h + 0x74 ; A2h+116
000001FA 7001 STRB R1,[R0,#0x0] ; A2h+116
65: A2h[112] &= 0xBF; // clear low alarm flag bit6
000001FC 4800 LDR R0,=A2h + 0x70 ; A2h+112
000001FE 7801 LDRB R1,[R0,#0x0] ; A2h+112
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