📄 config.lst
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ARM COMPILER V2.32a, config 08/08/05 09:50:21 PAGE 1
ARM COMPILER V2.32a, COMPILATION OF MODULE config
OBJECT MODULE PLACED IN config.OBJ
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe config.c THUMB OPTIMIZE(0,SPEED) BROWSE DEBUG TABS(4)
stmt level source
1 // cpu_config.c
2
3 /********************************************************************/
4 /* */
5 /* CPU Configurations */
6 /* */
7 /********************************************************************/
8
9 #include <ADuC7020.h>
10 #include "common.h"
11
12 void InitCPU()
13 {
14 1 // GPIO Port0 configuration
15 1 #if DEBUG == 0 // target is sfp board
16 1 GP0CON = 0x00000000; // P0.4(ExtIRQ0 - Tx FAIL)
17 1 // P0.5(ExtIRQ1 - Tx ALS)
18 1 // P0.6(LOS_INV)
19 1 #endif
20 1
21 1 #if DEBUG == 1 // target is aduc eval board
GP0CON = 0x10000000; // configure P0.7 as clock outputECLK)
#endif
24 1
25 1 GP0DAT = 0x40000000; // configure P0.6 as an output, set data LOW
26 1
27 1 // GPIO Port1 configuration
28 1 GP1CON = 0x00000022; // P1.0(SCL)
29 1 // P1.1(SDA)
30 1 // P1.2(GPIO - free)
31 1 // P1.3(GPIO - free)
32 1 // P1.4(GPIO - Rx LOS)
33 1 // P1.5(GPIO - RateSel)
34 1 // P1.6(GPIO - free)
35 1 // P1.7(GPIO - free)
36 1
37 1 #if DEBUG == 1
GP1DAT = 0x80000000; // configure P1.7 as an output
#endif
40 1
41 1 // GPIO Port2 configuration
42 1 GP2CON = 0x00000000; // P2.0(GPIO for SQUELCH)
43 1 GP2DAT = 0x01010000; // outputs high to enable SQUELCH(P2.0)
44 1 GP2CLR = 0x00010000; // outputs low to disable SQUELCH(P2.0)
45 1
46 1 // GPIO Port4 configuration (for test porpose)
47 1 #if DEBUG == 1
GP4DAT = 0x04000000; // configure P4.2 as an output
#endif
50 1
51 1 // I2C configuration
52 1 I2C0ID0 = 0xA0; // primary I2C address A0h
53 1 I2C0ID1 = 0xA2; // secondary I2C address A2h
54 1 I2C0CFG = 0x4201; // enable I2C slave, Stop IRQ, disable TX FIFO requst IRQ
55 1
56 1 // IRQ output configuration
57 1 PLAIRQ = 0x1700; // for stop detect using p1.0/p1.1
58 1
59 1 // Bandgap Reference configuration
ARM COMPILER V2.32a, config 08/08/05 09:50:21 PAGE 2
60 1 REFCON = 0x01; // use internal 2.5V reference
61 1
62 1 // ADC configuration
63 1 ADCCON = 0x20; // powerup ADC
64 1
65 1 // DAC configuration
66 1 DAC0CON = 0x12; // 0 to VREF DAC0 output range
67 1 DAC0DAT = 0x00000000; // DAC0 to 0V
68 1 DAC1CON = 0x12; // 0 to VREF DAC1 output range
69 1 DAC1DAT = 0x00000000; // DAC1 to 0V
70 1
71 1
72 1
73 1 // IRQ, FIQ setup (for GNU-GCC)
74 1 //IRQ = IRQ_Function; // specify Interrupt Service Rountine
75 1 //FIQ = FIQ_Function; // specify Interrupt Service Rountine
76 1
77 1 /* Use Timer2 when final silicon available
78 1 //Timer2 configuration
79 1 T2LD = 0x2000; // 1 / 32.768kHz * 8191 = 250ms
80 1 T2CON = 0xC0; // count down
81 1 // periodic mode
82 1 // binary format
83 1 // prescale:1, source clock/1
84 1 // source clock: internal 32.768KHz Oscillator
85 1 */
86 1
87 1 // Timer1 configuration
88 1 T1LD = 0x40; // 42000000/32768/20 (for overflow every 20Hz)
89 1 T1CON = 0xCF; // count down
90 1 // periodic mode
91 1 // binary format
92 1 // prescale:32768
93 1 // source clock: core clock
94 1 }
ARM COMPILER V2.32a, config 08/08/05 09:50:21 PAGE 3
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** PUBLICS:
PUBLIC InitCPU?T
*** CODE SEGMENT '?PR?InitCPU?T?config':
16: GP0CON = 0x00000000; // P0.4(ExtIRQ0 - Tx FAIL)
00000000 2100 MOV R1,#0x0
00000002 4800 LDR R0,=0xFFFFF400
00000004 6001 STR R1,[R0,#0x0]
25: GP0DAT = 0x40000000; // configure P0.6 as an output, set data LOW
00000006 4800 LDR R1,=0x40000000
00000008 4800 LDR R0,=0xFFFFF420
0000000A 6001 STR R1,[R0,#0x0]
28: GP1CON = 0x00000022; // P1.0(SCL)
0000000C 2122 MOV R1,#0x22
0000000E 4800 LDR R0,=0xFFFFF404
00000010 6001 STR R1,[R0,#0x0]
42: GP2CON = 0x00000000; // P2.0(GPIO for SQUELCH)
00000012 2100 MOV R1,#0x0
00000014 4800 LDR R0,=0xFFFFF408
00000016 6001 STR R1,[R0,#0x0]
43: GP2DAT = 0x01010000; // outputs high to enable SQUELCH(P2.0)
00000018 4800 LDR R1,=0x1010000
0000001A 4800 LDR R0,=0xFFFFF440
0000001C 6001 STR R1,[R0,#0x0]
44: GP2CLR = 0x00010000; // outputs low to disable SQUELCH(P2.0)
0000001E 4800 LDR R1,=0x10000
00000020 4800 LDR R0,=0xFFFFF448
00000022 6001 STR R1,[R0,#0x0]
52: I2C0ID0 = 0xA0; // primary I2C address A0h
00000024 21A0 MOV R1,#0xA0
00000026 4800 LDR R0,=0xFFFF0838
00000028 6001 STR R1,[R0,#0x0]
53: I2C0ID1 = 0xA2; // secondary I2C address A2h
0000002A 21A2 MOV R1,#0xA2
0000002C 4800 LDR R0,=0xFFFF083C
0000002E 6001 STR R1,[R0,#0x0]
54: I2C0CFG = 0x4201; // enable I2C slave, Stop IRQ, disable TX FIFO requst IRQ
00000030 4800 LDR R1,=0x4201
00000032 4800 LDR R0,=0xFFFF082C
00000034 6001 STR R1,[R0,#0x0]
57: PLAIRQ = 0x1700; // for stop detect using p1.0/p1.1
00000036 4800 LDR R1,=0x1700
00000038 4800 LDR R0,=0xFFFF0B44
0000003A 6001 STR R1,[R0,#0x0]
60: REFCON = 0x01; // use internal 2.5V reference
0000003C 2101 MOV R1,#0x1
0000003E 4800 LDR R0,=0xFFFF048C
00000040 6001 STR R1,[R0,#0x0]
63: ADCCON = 0x20; // powerup ADC
00000042 2120 MOV R1,#0x20
00000044 4800 LDR R0,=0xFFFF0500
00000046 6001 STR R1,[R0,#0x0]
66: DAC0CON = 0x12; // 0 to VREF DAC0 output range
00000048 2112 MOV R1,#0x12
0000004A 4800 LDR R0,=0xFFFF0600
0000004C 6001 STR R1,[R0,#0x0]
67: DAC0DAT = 0x00000000; // DAC0 to 0V
0000004E 2100 MOV R1,#0x0
00000050 4800 LDR R0,=0xFFFF0604
00000052 6001 STR R1,[R0,#0x0]
68: DAC1CON = 0x12; // 0 to VREF DAC1 output range
00000054 2112 MOV R1,#0x12
00000056 4800 LDR R0,=0xFFFF0608
ARM COMPILER V2.32a, config 08/08/05 09:50:21 PAGE 4
00000058 6001 STR R1,[R0,#0x0]
69: DAC1DAT = 0x00000000; // DAC1 to 0V
0000005A 2100 MOV R1,#0x0
0000005C 4800 LDR R0,=0xFFFF060C
0000005E 6001 STR R1,[R0,#0x0]
88: T1LD = 0x40; // 42000000/32768/20 (for overflow every 20Hz)
00000060 2140 MOV R1,#0x40
00000062 4800 LDR R0,=0xFFFF0320
00000064 6001 STR R1,[R0,#0x0]
89: T1CON = 0xCF; // count down
00000066 21CF MOV R1,#0xCF
00000068 4800 LDR R0,=0xFFFF0328
0000006A 6001 STR R1,[R0,#0x0]
94: }
0000006C 4770 BX R14
0000006E ENDP ; 'InitCPU?T'
Module Information Static
----------------------------------
code size = ------
data size = ------
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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