📄 main.lst
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ARM COMPILER V2.32a, main 08/08/05 09:50:21 PAGE 1
ARM COMPILER V2.32a, COMPILATION OF MODULE main
OBJECT MODULE PLACED IN main.OBJ
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe main.c THUMB OPTIMIZE(0,SPEED) BROWSE DEBUG TABS(4)
stmt level source
1 // main.c
2
3 /*************************************************************************
4 Program Name : SFP Reference Design Firmware
5 Hardware : SFP Module Board v1.3/V1.4, Host Board v1.0/v2.0
6 Parts on board : ADuC7019(rev.H Si)/ADN2870_1/ADN2890_1_2
7 Revision : 1.70 beta5
8 Date : Aug 3, 2005
9 Author : N.Matsuzoe
10 File(s) : main.c/config.c/monitor.c/diag.c/i2c.c/sff8472_table.c
11 ldd.c/irq.c/fiq.c/flash.c/common.h
12 Settings : Core Clock = 42MHz, CD=0, FINT=disable
13 DDM update rate = 50ms (Timer1@20Hz)
14 ER compensation update rate = 0.5s
15 Revision history:
16
17 r1.70b5(03Aug05) - added FEEMOD conifig, enabled read/write to flash
18 r1.70b4(03Aug05) - disabled read/write to Flash
19 r1.70b3(02Aug05) - added time out in Flash control
20
21 r1.70b1(28Jul05) - Support ADuC7019 REV.H silicon
22 - changed I2C routine
23 - removed PLA IRQ for a STOP detect
24 - changed temp sensor TC gain from -2mV/oC to -1.3mV/oC
25
26 r1.60(14Feb05) - Added slew rate control(5v/s) on DAC0 at start-up
27 - Changed I2C routine
28 - Added I2C stop detection by using Programable Logic Array
29 - Disabled auto flash update, changed flash update routine
30 - Changed LOS and RateSel detection. Using P1.4 and P1.5 as GPI
31 r1.52(23Nov04) - Changed TxPow ADC input channel from ADC3 to ADC15
32 r1.51(17Nov04) - Changed LOS_INV input to low
33 r1.50(28Oct04) - Support V1.3 and V1.4 PCB
34 Changed RxPow ADC input channel from ADC3 to ADC4
35 Changed TxPow ADC input channel from ADC4/14(Diff.) to ADC3(single-end)
36 r1.41(12Sep04) - Added software workaround for I2C device address decode error
37 Byte address from 0x80 thru 0xFF in i2c device address 0xA0
38 is not supported from this revision
39 r1.40(09Jul04) - Added write protection for read-only resister
40 Fixed checksum bug
41 r1.30(25Jun04) - Added closed-loop ER compensation function
42 Changed RxPowMonitor, support 2.0Kohm RSSI resistor
43 Added er#002 workaround
44 r1.20(14Jun04) - Support ADuC7020 REV.E silicon
45 Added I2C 2nd address match and I2C TX FIFO Flush
46 Fixed RxRateSel status bit
47 r1.17(10Jun04) - Added TxPowMon enable/disable resister
48 r1.16(03Jun04) - Added Checksum functions
49 Changed DDM data format, lower 4-bit fixed at zero
50 r1.15(27May04) - Disabled TxPow monitor
51 r1.14(26May04) - Changed TxPow monitor
52 r1.13(25May04) - Changed Timer freq., I2C_read and Temp Mon
53 r1.12(05May04) - Support ADuC7020 REV.D silicon
54 Added dummy ADC reads for all monior functions
55 r1.11(20Apr04) - Fixed temperature monitoring, ER compensation, RxPowMon
56 r1.10(13Apr04) - Added data save/load function by Flash/EE
57 r1.00(15Mar04) - Initial release, Support ADuC7020 REV.C silicon
58 **************************************************************************/
59
ARM COMPILER V2.32a, main 08/08/05 09:50:21 PAGE 2
60 #include <ADuC7020.h>
61 #include "common.h"
62
63 BYTE A0h[256];
64 BYTE A2h[256];
65 BYTE i2c_first, i2c_receive, dac_update;
66
67 int main(void){
68 1
69 1 FEEMOD |= 0x108; // enable flash erase/write
70 1
71 1 InitCPU(); // Initialize CPU configuration
72 1 InitFlash(); // Initialize Flash if first start-up(ProgramFlash-to-DataFlash)
73 1 InitSFF8472(); // Map SFF8472 table(DataFlash-to-SRAM)
74 1 InitLdd(); // Enable DAC for Er/Pav settting
75 1
76 1 i2c_first = TRUE;
77 1
78 1
79 1
80 1 FIQEN = 0x00000200; // enable I2C0SIRQ
81 1 IRQEN = 0x00048008; // enable Timer1IRQ, XIRQ0, XIRQ1
82 1
83 1 while(1){
84 2
85 2 #if DEBUG == 1
#endif
88 2
89 2 }
90 1 return (0);
91 1 }
ARM COMPILER V2.32a, main 08/08/05 09:50:21 PAGE 3
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN CODE16 (InitCPU?T)
EXTERN CODE16 (InitFlash?T)
EXTERN CODE16 (InitSFF8472?T)
EXTERN CODE16 (InitLdd?T)
EXTERN NUMBER (__startup)
*** PUBLICS:
PUBLIC main
PUBLIC A0h
PUBLIC A2h
PUBLIC i2c_first
PUBLIC i2c_receive
PUBLIC dac_update
*** DATA SEGMENT '?DT0?main':
00000000 A0h:
00000000 DS 256
00000100 A2h:
00000100 DS 256
00000200 i2c_first:
00000200 DS 1
00000201 i2c_receive:
00000201 DS 1
00000202 dac_update:
00000202 DS 1
*** CODE SEGMENT '?PR?main?main':
67: int main(void){
00000000 B500 PUSH {LR}
69: FEEMOD |= 0x108; // enable flash erase/write
00000002 4A42 LDR R2,=0x108
00000004 4800 LDR R0,=0xFFFFF804
00000006 6801 LDR R1,[R0,#0x0]
00000008 4311 ORR R1,R2
0000000A 6001 STR R1,[R0,#0x0]
71: InitCPU(); // Initialize CPU configuration
0000000C F7FF BL InitCPU?T ; T=0x0001 (1)
0000000E FFF8 BL InitCPU?T ; T=0x0001 (2)
72: InitFlash(); // Initialize Flash if first start-up(ProgramFlash-to-DataFlash)
00000010 F7FF BL InitFlash?T ; T=0x0001 (1)
00000012 FFF6 BL InitFlash?T ; T=0x0001 (2)
73: InitSFF8472(); // Map SFF8472 table(DataFlash-to-SRAM)
00000014 F7FF BL InitSFF8472?T ; T=0x0001 (1)
00000016 FFF4 BL InitSFF8472?T ; T=0x0001 (2)
74: InitLdd(); // Enable DAC for Er/Pav settting
00000018 F7FF BL InitLdd?T ; T=0x0001 (1)
0000001A FFF2 BL InitLdd?T ; T=0x0001 (2)
76: i2c_first = TRUE;
0000001C 2101 MOV R1,#0x1
0000001E 4800 LDR R0,=i2c_first ; i2c_first
00000020 7001 STRB R1,[R0,#0x0] ; i2c_first
80: FIQEN = 0x00000200; // enable I2C0SIRQ
00000022 4980 LDR R1,=0x200
00000024 4800 LDR R0,=0xFFFF0108
00000026 6001 STR R1,[R0,#0x0]
81: IRQEN = 0x00048008; // enable Timer1IRQ, XIRQ0, XIRQ1
00000028 4800 LDR R1,=0x48008
0000002A 4800 LDR R0,=0xFFFF0008
0000002C 6001 STR R1,[R0,#0x0]
89: }
0000002E L_1:
0000002E E7FE B L_1 ; T=0x0000002E
ARM COMPILER V2.32a, main 08/08/05 09:50:21 PAGE 4
90: return (0);
00000030 2000 MOV R0,#0x0
91: }
00000032 BC08 POP {R3}
00000034 4718 BX R3
00000036 ENDP ; 'main'
Module Information Static
----------------------------------
code size = ------
data size = 515
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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