📄 fiq.lst
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000000D0 E5C89000 STRB R9,[R8,#0x0] ; byte_addr2
34: I2CSTX = A2h[byte_addr2]; // set TX data
000000D4 E5108000 LDR R0,=byte_addr2 ; byte_addr2
000000D8 E5D88000 LDRB R8,[R8,#0x0] ; byte_addr2
000000DC E1A09008 MOV R9,R8
000000E0 E5108000 LDR R0,=A2h ; A2h
000000E4 E0888009 ADD R8,R8,R9 ; A2h
000000E8 E5D88000 LDRB R8,[R8,#0x0]
000000EC E1A09008 MOV R9,R8
000000F0 E5108000 LDR R0,=0xFFFF080C
000000F4 E5889000 STR R9,[R8,#0x0]
35: }
000000F8 L_3:
36: I2CCFG = 0x4001; // clear bit9, enable Slave Tx FIFO request interrupt
000000F8 E5109000 LDR R1,=0x4001
000000FC E5108000 LDR R0,=0xFFFF082C
00000100 E5889000 STR R9,[R8,#0x0]
37: }
00000104 L_1:
40: if((status & 0x0008) == 0x0008){ // slave receiver intterupt
00000104 E28D8000 ADD R8,R13,#0x0000
00000108 E5988000 LDR R8,[R8,#0x0] ; status
0000010C E3180008 TST R8,#0x0008
00000110 0A00004D BEQ L_4 ; Targ=0x24C
42: if(i2c_first == TRUE){ // first slave-receiver INT?
00000114 E5108000 LDR R0,=i2c_first ; i2c_first
00000118 E5D88000 LDRB R8,[R8,#0x0] ; i2c_first
0000011C E3580001 CMP R8,#0x0001
00000120 1A000010 BNE L_5 ; Targ=0x168
43: if((status&0x1800)==0) byte_addr0=I2CSRX; // get byte address
00000124 E28D8000 ADD R8,R13,#0x0000
00000128 E5988000 LDR R8,[R8,#0x0] ; status
0000012C E3180B06 TST R8,#0x1800
00000130 1A000004 BNE L_6 ; Targ=0x148
00000134 E5108000 LDR R0,=0xFFFF0808
00000138 E5989000 LDR R9,[R8,#0x0]
0000013C E5108000 LDR R0,=byte_addr0 ; byte_addr0
00000140 E5C89000 STRB R9,[R8,#0x0] ; byte_addr0
00000144 EA000003 B L_7 ; Targ=0x158
00000148 L_6:
44: else byte_addr2 = I2CSRX;
00000148 E5108000 LDR R0,=0xFFFF0808
0000014C E5989000 LDR R9,[R8,#0x0]
ARM COMPILER V2.32a, fiq 08/08/05 09:50:23 PAGE 5
00000150 E5108000 LDR R0,=byte_addr2 ; byte_addr2
00000154 E5C89000 STRB R9,[R8,#0x0] ; byte_addr2
00000158 L_7:
45: i2c_first = FALSE;
00000158 E3A09000 MOV R9,#0x0
0000015C E5108000 LDR R0,=i2c_first ; i2c_first
00000160 E5C89000 STRB R9,[R8,#0x0] ; i2c_first
46: }
00000164 EA000038 B L_4 ; Targ=0x24C
00000168 L_5:
49: if((status&0x1800)==0){
00000168 E28D8000 ADD R8,R13,#0x0000
0000016C E5988000 LDR R8,[R8,#0x0] ; status
00000170 E3180B06 TST R8,#0x1800
00000174 1A00000F BNE L_9 ; Targ=0x1B8
50: A0h[byte_addr0] = I2CSRX; // get byte data
00000178 E5108000 LDR R0,=0xFFFF0808
0000017C E5989000 LDR R9,[R8,#0x0]
00000180 E5108000 LDR R0,=byte_addr0 ; byte_addr0
00000184 E5D88000 LDRB R8,[R8,#0x0] ; byte_addr0
00000188 E1A0A008 MOV R10,R8
0000018C E5108000 LDR R0,=A0h ; A0h
00000190 E088800A ADD R8,R8,R10 ; A0h
00000194 E5C89000 STRB R9,[R8,#0x0]
51: byte_addr0++; // increment address
00000198 E5108000 LDR R0,=byte_addr0 ; byte_addr0
0000019C E5D89000 LDRB R9,[R8,#0x0] ; byte_addr0
000001A0 E2899001 ADD R9,R9,#0x0001
000001A4 E5C89000 STRB R9,[R8,#0x0] ; byte_addr0
52: i2c_receive = 0xA0;
000001A8 E3A090A0 MOV R9,#0xA0
000001AC E5108000 LDR R0,=i2c_receive ; i2c_receive
000001B0 E5C89000 STRB R9,[R8,#0x0] ; i2c_receive
53: }
000001B4 EA000024 B L_4 ; Targ=0x24C
000001B8 L_9:
55: A2h[byte_addr2] = I2CSRX; // save received byte data
000001B8 E5108000 LDR R0,=0xFFFF0808
000001BC E5989000 LDR R9,[R8,#0x0]
000001C0 E5108000 LDR R0,=byte_addr2 ; byte_addr2
000001C4 E5D88000 LDRB R8,[R8,#0x0] ; byte_addr2
000001C8 E1A0A008 MOV R10,R8
000001CC E5108000 LDR R0,=A2h ; A2h
000001D0 E088800A ADD R8,R8,R10 ; A2h
000001D4 E5C89000 STRB R9,[R8,#0x0]
56: if((byte_addr2==248)||(byte_addr2==249)) dac_update=1;
000001D8 E5108000 LDR R0,=byte_addr2 ; byte_addr2
000001DC E5D88000 LDRB R8,[R8,#0x0] ; byte_addr2
000001E0 E35800F8 CMP R8,#0x00F8
000001E4 0A000003 BEQ L_12 ; Targ=0x1F8
000001E8 E5108000 LDR R0,=byte_addr2 ; byte_addr2
000001EC E5D88000 LDRB R8,[R8,#0x0] ; byte_addr2
000001F0 E35800F9 CMP R8,#0x00F9
000001F4 1A000002 BNE L_11 ; Targ=0x204
000001F8 L_12:
000001F8 E3A09001 MOV R9,#0x1
000001FC E5108000 LDR R0,=dac_update ; dac_update
00000200 E5C89000 STRB R9,[R8,#0x0] ; dac_update
00000204 L_11:
57: if((byte_addr2==250)||(byte_addr2==251)) dac_update=2;
00000204 E5108000 LDR R0,=byte_addr2 ; byte_addr2
00000208 E5D88000 LDRB R8,[R8,#0x0] ; byte_addr2
0000020C E35800FA CMP R8,#0x00FA
00000210 0A000003 BEQ L_14 ; Targ=0x224
00000214 E5108000 LDR R0,=byte_addr2 ; byte_addr2
00000218 E5D88000 LDRB R8,[R8,#0x0] ; byte_addr2
ARM COMPILER V2.32a, fiq 08/08/05 09:50:23 PAGE 6
0000021C E35800FB CMP R8,#0x00FB
00000220 1A000002 BNE L_13 ; Targ=0x230
00000224 L_14:
00000224 E3A09002 MOV R9,#0x2
00000228 E5108000 LDR R0,=dac_update ; dac_update
0000022C E5C89000 STRB R9,[R8,#0x0] ; dac_update
00000230 L_13:
58: byte_addr2++;
00000230 E5108000 LDR R0,=byte_addr2 ; byte_addr2
00000234 E5D89000 LDRB R9,[R8,#0x0] ; byte_addr2
00000238 E2899001 ADD R9,R9,#0x0001
0000023C E5C89000 STRB R9,[R8,#0x0] ; byte_addr2
59: i2c_receive = 0xA2;
00000240 E3A090A2 MOV R9,#0xA2
00000244 E5108000 LDR R0,=i2c_receive ; i2c_receive
00000248 E5C89000 STRB R9,[R8,#0x0] ; i2c_receive
62: }
0000024C L_4:
65: if((status & 0x0400) == 0x0400){ // STOP detect
0000024C E28D8000 ADD R8,R13,#0x0000
00000250 E5988000 LDR R8,[R8,#0x0] ; status
00000254 E3180B01 TST R8,#0x0400
00000258 0A00001B BEQ L_15 ; Targ=0x2CC
66: I2C0FSTA |= 0x100; // flush TX FIFO
0000025C E5108000 LDR R0,=0xFFFF084C
00000260 E5989000 LDR R9,[R8,#0x0]
00000264 E3899C01 ORR R9,R9,#0x0100
00000268 E5889000 STR R9,[R8,#0x0]
67: i2c_first = TRUE;
0000026C E3A09001 MOV R9,#0x1
00000270 E5108000 LDR R0,=i2c_first ; i2c_first
00000274 E5C89000 STRB R9,[R8,#0x0] ; i2c_first
68: if(I2CCFG == 0x4001){
00000278 E5108000 LDR R0,=0xFFFF082C
0000027C E5988000 LDR R8,[R8,#0x0]
00000280 E5109000 LDR R1,=0x4001
00000284 E1580009 CMP R8,R9
00000288 1A00000F BNE L_15 ; Targ=0x2CC
69: if((status&0x1800)==0)byte_addr0--; // decrement byte address
0000028C E28D8000 ADD R8,R13,#0x0000
00000290 E5988000 LDR R8,[R8,#0x0] ; status
00000294 E3180B06 TST R8,#0x1800
00000298 1A000004 BNE L_17 ; Targ=0x2B0
0000029C E5108000 LDR R0,=byte_addr0 ; byte_addr0
000002A0 E5D89000 LDRB R9,[R8,#0x0] ; byte_addr0
000002A4 E2499001 SUB R9,R9,#0x0001
000002A8 E5C89000 STRB R9,[R8,#0x0] ; byte_addr0
000002AC EA000003 B L_18 ; Targ=0x2C0
000002B0 L_17:
70: else byte_addr2--;
000002B0 E5108000 LDR R0,=byte_addr2 ; byte_addr2
000002B4 E5D89000 LDRB R9,[R8,#0x0] ; byte_addr2
000002B8 E2499001 SUB R9,R9,#0x0001
000002BC E5C89000 STRB R9,[R8,#0x0] ; byte_addr2
000002C0 L_18:
71: I2CCFG = 0x4201; // set bit9, clear Slave Tx FIFO request interrupt
000002C0 E5109000 LDR R1,=0x4201
000002C4 E5108000 LDR R0,=0xFFFF082C
000002C8 E5889000 STR R9,[R8,#0x0]
73: }
000002CC L_15:
79: return;
000002CC ; SCOPE-END
81: }
000002CC E28DD004 ADD R13,R13,#0x0004
000002D0 E25EF004 SUBS R15,R14,#0x0004
ARM COMPILER V2.32a, fiq 08/08/05 09:50:23 PAGE 7
000002D4 ENDP ; 'FIQ_Handler?A'
Module Information Static
----------------------------------
code size = ------
data size = 2
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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