📄 fiq.lst
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ARM COMPILER V2.32a, fiq 08/08/05 09:50:23 PAGE 1
ARM COMPILER V2.32a, COMPILATION OF MODULE fiq
OBJECT MODULE PLACED IN fiq.OBJ
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe fiq.c THUMB OPTIMIZE(0,SPEED) BROWSE DEBUG TABS(4)
stmt level source
1 // fiq.c
2 /********************************************************************/
3 /* */
4 /* FIQ ISR */
5 /* */
6 /********************************************************************/
7
8 #include <ADuC7020.h>
9 #include "common.h"
10
11
12 void FIQ_Handler (void) __fiq {
13 1
14 1 static BYTE byte_addr0 = 0x00;
15 1 static BYTE byte_addr2 = 0x00;
16 1 int status = I2CSSTA;
17 1
18 1 #if DEBUG == 1
GP1SET = 0x00800000;
#endif
21 1
22 1
23 1 /***** Slave TX *****/
24 1 if((status & 0x0004) == 0x0004){ // slave transmitter interrupt?
25 2 I2C0FSTA |= 0x100; // flush TX FIFO
26 2 if((status&0x1800)==0){ // ID decode bit is 00?
27 3 I2CSTX = A0h[byte_addr0]; // set TX data
28 3 byte_addr0++; // increment byte address
29 3 I2CSTX = A0h[byte_addr0]; // set TX data
30 3 }
31 2 else{
32 3 I2CSTX = A2h[byte_addr2]; // set TX data
33 3 byte_addr2++; // increment byte address
34 3 I2CSTX = A2h[byte_addr2]; // set TX data
35 3 }
36 2 I2CCFG = 0x4001; // clear bit9, enable Slave Tx FIFO request inter
-rupt
37 2 }
38 1
39 1 /***** Slave RX *****/
40 1 if((status & 0x0008) == 0x0008){ // slave receiver intterupt
41 2
42 2 if(i2c_first == TRUE){ // first slave-receiver INT?
43 3 if((status&0x1800)==0) byte_addr0=I2CSRX; // get byte address
44 3 else byte_addr2 = I2CSRX;
45 3 i2c_first = FALSE;
46 3 }
47 2
48 2 else{
49 3 if((status&0x1800)==0){
50 4 A0h[byte_addr0] = I2CSRX; // get byte data
51 4 byte_addr0++; // increment address
52 4 i2c_receive = 0xA0;
53 4 }
54 3 else{
55 4 A2h[byte_addr2] = I2CSRX; // save received byte data
56 4 if((byte_addr2==248)||(byte_addr2==249)) dac_update=1;
57 4 if((byte_addr2==250)||(byte_addr2==251)) dac_update=2;
58 4 byte_addr2++;
ARM COMPILER V2.32a, fiq 08/08/05 09:50:23 PAGE 2
59 4 i2c_receive = 0xA2;
60 4 }
61 3 }
62 2 }
63 1
64 1 /***** Stop Condition *****/
65 1 if((status & 0x0400) == 0x0400){ // STOP detect
66 2 I2C0FSTA |= 0x100; // flush TX FIFO
67 2 i2c_first = TRUE;
68 2 if(I2CCFG == 0x4001){
69 3 if((status&0x1800)==0)byte_addr0--; // decrement byte address
70 3 else byte_addr2--;
71 3 I2CCFG = 0x4201; // set bit9, clear Slave Tx FIFO request interrup
-t
72 3 }
73 2 }
74 1
75 1 #if DEBUG == 1
GP1CLR = 0x00800000;
#endif
78 1
79 1 return;
80 1
81 1 }
82
ARM COMPILER V2.32a, fiq 08/08/05 09:50:23 PAGE 3
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN DATA (A0h)
EXTERN DATA (A2h)
EXTERN DATA (i2c_first)
EXTERN DATA (i2c_receive)
EXTERN DATA (dac_update)
*** PUBLICS:
PUBLIC FIQ_Handler?A
*** DATA SEGMENT '?DT0?fiq':
00000000 byte_addr0:
00000000 BEGIN_INIT
00000000 00 DB 0x0
00000001 END_INIT
00000001 byte_addr2:
00000001 BEGIN_INIT
00000001 00 DB 0x0
00000002 END_INIT
*** CODE SEGMENT '?PR?FIQ_Handler?A?fiq':
12: void FIQ_Handler (void) __fiq {
00000000 E24DD004 SUB R13,R13,#0x0004
00000004 ; SCOPE-START
16: int status = I2CSSTA;
00000004 E5108000 LDR R0,=0xFFFF0804
00000008 E5989000 LDR R9,[R8,#0x0]
0000000C E28D8000 ADD R8,R13,#0x0000
00000010 E5889000 STR R9,[R8,#0x0] ; status
24: if((status & 0x0004) == 0x0004){ // slave transmitter interrupt?
00000014 E28D8000 ADD R8,R13,#0x0000
00000018 E5988000 LDR R8,[R8,#0x0] ; status
0000001C E3180004 TST R8,#0x0004
00000020 0A000037 BEQ L_1 ; Targ=0x104
25: I2C0FSTA |= 0x100; // flush TX FIFO
00000024 E5108000 LDR R0,=0xFFFF084C
00000028 E5989000 LDR R9,[R8,#0x0]
0000002C E3899C01 ORR R9,R9,#0x0100
00000030 E5889000 STR R9,[R8,#0x0]
26: if((status&0x1800)==0){ // ID decode bit is 00?
00000034 E28D8000 ADD R8,R13,#0x0000
00000038 E5988000 LDR R8,[R8,#0x0] ; status
0000003C E3180B06 TST R8,#0x1800
00000040 1A000016 BNE L_2 ; Targ=0xA0
27: I2CSTX = A0h[byte_addr0]; // set TX data
00000044 E5108000 LDR R0,=byte_addr0 ; byte_addr0
00000048 E5D88000 LDRB R8,[R8,#0x0] ; byte_addr0
0000004C E1A09008 MOV R9,R8
00000050 E5108000 LDR R0,=A0h ; A0h
00000054 E0888009 ADD R8,R8,R9 ; A0h
00000058 E5D88000 LDRB R8,[R8,#0x0]
0000005C E1A09008 MOV R9,R8
00000060 E5108000 LDR R0,=0xFFFF080C
00000064 E5889000 STR R9,[R8,#0x0]
28: byte_addr0++; // increment byte address
00000068 E5108000 LDR R0,=byte_addr0 ; byte_addr0
0000006C E5D89000 LDRB R9,[R8,#0x0] ; byte_addr0
00000070 E2899001 ADD R9,R9,#0x0001
00000074 E5C89000 STRB R9,[R8,#0x0] ; byte_addr0
29: I2CSTX = A0h[byte_addr0]; // set TX data
00000078 E5108000 LDR R0,=byte_addr0 ; byte_addr0
0000007C E5D88000 LDRB R8,[R8,#0x0] ; byte_addr0
00000080 E1A09008 MOV R9,R8
ARM COMPILER V2.32a, fiq 08/08/05 09:50:23 PAGE 4
00000084 E5108000 LDR R0,=A0h ; A0h
00000088 E0888009 ADD R8,R8,R9 ; A0h
0000008C E5D88000 LDRB R8,[R8,#0x0]
00000090 E1A09008 MOV R9,R8
00000094 E5108000 LDR R0,=0xFFFF080C
00000098 E5889000 STR R9,[R8,#0x0]
30: }
0000009C EA000015 B L_3 ; Targ=0xF8
000000A0 L_2:
32: I2CSTX = A2h[byte_addr2]; // set TX data
000000A0 E5108000 LDR R0,=byte_addr2 ; byte_addr2
000000A4 E5D88000 LDRB R8,[R8,#0x0] ; byte_addr2
000000A8 E1A09008 MOV R9,R8
000000AC E5108000 LDR R0,=A2h ; A2h
000000B0 E0888009 ADD R8,R8,R9 ; A2h
000000B4 E5D88000 LDRB R8,[R8,#0x0]
000000B8 E1A09008 MOV R9,R8
000000BC E5108000 LDR R0,=0xFFFF080C
000000C0 E5889000 STR R9,[R8,#0x0]
33: byte_addr2++; // increment byte address
000000C4 E5108000 LDR R0,=byte_addr2 ; byte_addr2
000000C8 E5D89000 LDRB R9,[R8,#0x0] ; byte_addr2
000000CC E2899001 ADD R9,R9,#0x0001
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