📄 priority.vhd
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-- coder is described in this projiect
-- D0~D7 are input vectors
-- Q0~Q2 are the output of the cording
--------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity priority is
port(D : in bit_vector(0 to 7); --inputs to be prioritised
E1 : in bit;
Q : out bit_vector(0 to 2); --encoded output
E0 : out bit;
GS : out bit); --group signal output
end priority;
-------------------------------------------------------------------
architecture coder of priority is
begin
process(D,E0)
begin
if E1 = '1'then
GS <= '1'; --set default outputs
E0 <= '1';
Q <= "111";
elsif D(7) = '0' then
Q<= "000";
GS <= '0';
E0 <= '1';
elsif D(6) = '0' then
Q <= "001";
GS <= '0';
E0 <= '1';
elsif D(5) = '0' then
Q <= "010";
GS <= '0';
E0 <= '1';
elsif D(4) = '0' then
Q <= "011";
GS <='0';
E0 <= '1';
elsif D(3) = '0' then
Q <= "100";
GS <='0';
E0 <= '1';
elsif D(2) = '0' then
Q <= "101";
GS <='0';
E0 <= '1';
elsif D(1) = '0' then
Q <= "110";
GS <='0';
E0 <= '1';
elsif I(0) = '0' then
Q <= "111";
GS <='0';
E0 <= '1';
else
Q <="111";
GS <= '1';
E0 <= '0';
end if;
end process;
end coder;
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