counter.vhd

来自「128-64点阵液晶模块的显示程序带反显平移等功能.rar,非常实用.」· VHDL 代码 · 共 49 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY COUNTER IS
PORT
	(
		BCDIN	: IN	INTEGER RANGE 0 TO 9;
		BCDWR1	: IN	STD_LOGIC;
		BCDWR10	: IN	STD_LOGIC;
		CLK		: IN   	STD_LOGIC;
		CIN		: IN	STD_LOGIC;
		CO		: OUT	STD_LOGIC;
		BCD1OUT	: OUT 	INTEGER RANGE 0 TO 9;
		BCD10OUT: OUT	INTEGER RANGE 0 TO 6);
	
END COUNTER;

ARCHITECTURE A OF COUNTER IS
	SIGNAL	COUNT1	: INTEGER RANGE 0 TO 9;
	SIGNAL	COUNT10	: INTEGER RANGE 0 TO 5;
BEGIN
	PROCESS (CLK,BCDWR1,BCDWR10)
	BEGIN
		IF ( CLK'EVENT AND CLK = '1') THEN
			IF BCDWR1= '1' THEN
				COUNT1 <= BCDIN;
			ELSIF BCDWR10= '1'THEN
				COUNT10 <= BCDIN;
			ELSIF CIN='1' THEN
				IF (COUNT1 = 9)THEN
					COUNT1 <=0;
					IF COUNT10 = 5 THEN
						COUNT10 <=0;
					ELSE
						COUNT10 <= COUNT10 +1;
					END IF;
				ELSE	
					COUNT1 <= COUNT1 + 1;
				END IF;
			END IF;
		END IF;
	END PROCESS;
	CO <= '1' WHEN COUNT1=0 AND COUNT10 =0 ELSE '0';
	BCD1OUT <= COUNT1;
	BCD10OUT <= COUNT10;
END a;