mpc8260.h

powerpc82xx mcc driver

  VUWORD  rptr;           /* Rx internal data pointer */
  VUHWORD rbptr;          /* rb BD Pointer */
  VUHWORD rcount;         /* Rx internal byte count */
  VUWORD  rtemp;          /* Rx temp */
  VUWORD  tstate;         /* Tx internal state */
  VUWORD  tptr;           /* Tx internal data pointer */
  VUHWORD tbptr;          /* Tx BD pointer */
  VUHWORD tcount;         /* Tx byte count */
  VUWORD  ttemp;          /* Tx temp */
    
  /* SMC VUART-specific PRAM */
  VUHWORD max_idl;        /* Maximum IDLE Characters */
  VUHWORD idlc;           /* Temporary IDLE Counter */
  VUHWORD brkln;          /* Last Rx Break Length */
  VUHWORD brkec;          /* Rx Break Condition Counter */
  VUHWORD brkcr;          /* Break Count Register (Tx) */
  VUHWORD r_mask;         /* Temporary bit mask */  
}  /* _PackedType */ t_Smc_Pram;



/*---------------------------------------------------------------------------*/
/*                            IDMA PARAMETER RAM                             */
/*---------------------------------------------------------------------------*/

typedef  struct  
{
  VUHWORD ibase;          /* IDMA BD Base Address */
  VUHWORD dcm;            /* DMA channel mode register */
  VUHWORD ibdptr;         /* next bd ptr */
  VUHWORD DPR_buf;        /* ptr to internal 64 byte buffer */
  VUHWORD BUF_inv;        /* The quantity of data in DPR_buf */
  VUHWORD SS_max;         /* Steady State Max. transfer size */
  VUHWORD DPR_in_ptr;     /* write ptr for the internal buffer */
  VUHWORD sts;            /* Source Transfer Size */
  VUHWORD DPR_out_ptr;    /* read ptr for the internal buffer */
  VUHWORD seob;           /* Source end of burst */
  VUHWORD deob;           /* Destination end of burst */
  VUHWORD dts;            /* Destination Transfer Size */
  VUHWORD RetAdd;         /* return address when ERM==1 */
  VUHWORD Reserved;       /* reserved */
  VUWORD  BD_cnt;         /* Internal byte count */
  VUWORD  S_ptr;          /* source internal data ptr */
  VUWORD  D_ptr;          /* destination internal data ptr */
  VUWORD  istate;         /* Internal state */
}  /* _PackedType */ t_Idma_Pram;



/*-------------------------------------------------------------------*/
/*                    INTER-INTEGRATED CIRCUIT  (I2C)                */
/*-------------------------------------------------------------------*/

typedef  struct 
{
  VUHWORD rbase;          /* RX BD base address */
  VUHWORD tbase;          /* TX BD base address */
  VUBYTE  rfcr;           /* Rx function code */
  VUBYTE  tfcr;           /* Tx function code */
  VUHWORD mrblr;          /* Rx buffer length */
  VUWORD  rstate;         /* Rx internal state */
  VUWORD  rptr;           /* Rx internal data pointer */
  VUHWORD rbptr;          /* rb BD Pointer */
  VUHWORD rcount;         /* Rx internal byte count */
  VUWORD  rtemp;          /* Rx temp */
  VUWORD  tstate;         /* Tx internal state */
  VUWORD  tptr;           /* Tx internal data pointer */
  VUHWORD tbptr;          /* Tx BD pointer */
  VUHWORD tcount;         /* Tx byte count */
  VUWORD  ttemp;          /* Tx temp */
}  /* _PackedType */ t_I2c_Pram;



/*---------------------------------------------------------------------------*/
/*                       SERIAL PERIPHERAL INTERFACE  (SPI)                  */
/*---------------------------------------------------------------------------*/

typedef  struct  
{
  VUHWORD rbase;          /* Rx BD Base Address */
  VUHWORD tbase;          /* Tx BD Base Address */
  VUBYTE  rfcr;           /* Rx function code */
  VUBYTE  tfcr;           /* Tx function code */
  VUHWORD mrblr;          /* Rx buffer length */
  VUWORD  rstate;         /* Rx internal state */
  VUWORD  rptr;           /* Rx internal data pointer */
  VUHWORD rbptr;          /* Rx BD Pointer */
  VUHWORD rcount;         /* Rx internal byte count */
  VUWORD  rtemp;          /* Rx temp */
  VUWORD  tstate;         /* Tx internal state */
  VUWORD  tptr;           /* Tx internal data pointer */
  VUHWORD tbptr;          /* Tx BD pointer */
  VUHWORD tcount;         /* Tx byte count */
  VUWORD  ttemp;          /* Tx temp */
  VUBYTE  reserved[8];
}  /* _PackedType */ t_Spi_Pram;



/*---------------------------------------------------------------------------*/
/*                      RISC TIMER PARAMETER RAM                             */
/*---------------------------------------------------------------------------*/

typedef  struct  
{
 
  VUHWORD tm_base;        /* RISC timer table base adr */
  VUHWORD tm_ptr;         /* RISC timer table pointer */
  VUHWORD r_tmr;          /* RISC timer mode register */
  VUHWORD r_tmv;          /* RISC timer valid register */
  VUWORD  tm_cmd;         /* RISC timer cmd register */
  VUWORD  tm_cnt;         /* RISC timer internal cnt */
}  /* _PackedType */ t_timer_pram;



/*--------------------------------------------------------------------------*/
/*                  ROM MICROCODE PARAMETER RAM AREA                        */
/*--------------------------------------------------------------------------*/

typedef  struct  
{
  VUHWORD rev_num;        /* VUcode Revision Number */
  VUHWORD d_ptr;          /* MISC Dump area pointer */
}  /* _PackedType */ t_ucode_pram;








/*--------------------------------------------------------------------------*/
/*                MAIN DEFINITION OF MPC8260 INTERNAL MEMORY MAP            */
/*--------------------------------------------------------------------------*/

typedef  struct 
{

  /* cpm_ram */
  t_Mch_Pram  mch_pram[256];      /* MCC logical channels parameter ram */
  VUBYTE      reserved0[0x4000];  /* Reserved area */
    
  /* DPR_BASE+0x8000*/

  /*---------------------------------------------------------------------*/
  /* A note about the pram union:                                        */
  /* The pram area has been broken out three ways for clean access into  */
  /* certain peripherals' spaces.  This arrangement allows programmers   */
  /* flexibility of usage in terms of being able to change which         */
  /* peripheral is being accessed by simply changing an array value.     */
  /* Given the interweaving of certain peripherals' pram areas, this     */
  /* would not be possible with only one large pram structure.           */
  /*                                                                     */
  /* SERIALS  - For accessing SCC, non-ATM FCC, and MCC pram             */
  /* ATM      - For accessing ATM FCC pram                               */
  /* STANDARD - For accessing timers, revnum, d_ptr, RAND, and the pram  */
  /*            base pointers of the SMCs, IDMAs, SPI, and I2C           */
  /*---------------------------------------------------------------------*/
           
  union 
  {
    
    /*for access to the PRAM structs for SCCs, FCCs, and MCCs */ 
    struct serials 
    {
      t_Scc_Pram scc_pram[4];
      t_Fcc_Pram fcc_pram[3];
      t_Mcc_Pram mcc_pram[2];
      /*           VUBYTE reserved1[0x700];   */
    } serials;
        
    /* for access to ATM PRAM structs */
    struct atm
    {
      VUBYTE reserved2[0x400];
      t_Atm_Pram atm_pram[2];
      /*           VUBYTE reserved3[0xa00]; */
    } atm;
        
    /* for access to the memory locations holding user-defined 
       base addresses of PRAM for SMCs, IDMA, SPI, and I2C. */     
    struct standard
    {
      VUBYTE scc1[0x100];
      VUBYTE scc2[0x100];
      VUBYTE scc3[0x100];
      VUBYTE scc4[0x100];
      VUBYTE fcc1[0x100];
      VUBYTE fcc2[0x100];
      VUBYTE fcc3[0x100];
      VUBYTE mcc1[0x80];
      VUBYTE reserved_0[0x7c];
      VUBYTE smc1[0x2];
      VUBYTE idma1[0x2];
      VUBYTE mcc2[0x80];
      VUBYTE reserved_1[0x7c];
      VUBYTE smc2[0x2];
      VUBYTE idma2[0x2];
      VUBYTE reserved_2[0xfc];
      VUBYTE spi[0x2];
      VUBYTE idma3[0x2];
      VUBYTE reserved_3[0xe0];
      VUBYTE timers[0x10];
      VUBYTE Rev_num[0x2];
      VUBYTE D_ptr[0x2];
      VUBYTE reserved_4[0x4];
      VUBYTE rand[0x4];
      VUBYTE i2c[0x2];
      VUBYTE idma4[0x2];
      VUBYTE reserved_5[0x500];
    } standard;
        
  }  /* _PackedType */ pram;
    
  VUBYTE  reserved11[0x2000];      /* Reserved area */
  VUBYTE  cpm_ram_dpram_2[0x1000]; /* Internal RAM */
  VUBYTE  reserved12[0x4000];      /* Reserved area */

  /* siu */
  VUWORD  siu_siumcr;         /* SIU Module Configuration Register */
  VUWORD  siu_sypcr;          /* System Protection Control Register */
  VUBYTE  reserved13[0x6];    /* Reserved area */
  VUHWORD siu_swsr;           /* Software Service Register */

  /* buses */
  VUBYTE  reserved14[0x14];   /* Reserved area */
  VUWORD  bcr;                /* Bus Configuration Register */
  VUBYTE  ppc_acr;            /* Arbiter Configuration Register */
  VUBYTE  reserved15[0x3];    /* Reserved area */
  VUWORD  ppc_alrh;           /* Arbitration Level Reg. (First clients)*/
  VUWORD  ppc_alrl;           /* Arbitration Level Reg. (Next clients) */
  VUBYTE  lcl_acr;            /* LCL Arbiter Configuration Register */
  VUBYTE  reserved16[0x3];    /* Reserved area */
  VUWORD  lcl_alrh;      /* LCL Arbitration Level Reg. (First clients) */
  VUWORD  lcl_alrl;      /* LCL Arbitration Level Register (Next clients) */
  VUWORD  tescr1;        /* PPC bus transfer error status control reg. 1 */
  VUWORD  tescr2;        /* PPC bus transfer error status control reg. 2 */
  VUWORD  ltescr1;       /* Local bus transfer error status control reg. 1 */
  VUWORD  ltescr2;       /* Local bus transfer error status control reg. 2 */
  VUWORD  pdtea;              /* PPC bus DMA Transfer Error Address */
  VUBYTE  pdtem;              /* PPC bus DMA Transfer Error MSNUM  */
  VUBYTE  reserved17[0x3];    /* Reserved area */
  VUWORD  ldtea;              /* PPC bus DMA Transfer Error Address */
  VUBYTE  ldtem;              /* PPC bus DMA Transfer Error MSNUM  */
  VUBYTE  reserved18[0xa3];   /* Reserved area */

  /* memc */
  struct memc_regs 
  {
    VUWORD br;              /* Base Register */
    VUWORD or;              /* Option Register */
  } memc_regs[12];
  VUBYTE  reserved19[0x8];    /* Reserved area */
  VUWORD  memc_mar;           /* Memory Address Register */
  VUBYTE  reserved20[0x4];    /* Reserved area */
  VUWORD  memc_mamr;          /* Machine A Mode Register */
  VUWORD  memc_mbmr;          /* Machine B Mode Register */
  VUWORD  memc_mcmr;          /* Machine C Mode Register */
  VUWORD  memc_mdmr;          /* Machine D Mode Register */
  VUBYTE  reserved21[0x4];    /* Reserved area */
  VUHWORD memc_mptpr;         /* Memory Periodic Timer Prescaler */
  VUBYTE  reserved22[0x2];    /* Reserved area */
  VUWORD  memc_mdr;           /* Memory Data Register */
  VUBYTE  reserved23[0x4];    /* Reserved area */
  VUWORD  memc_psdmr;         /* PowerPC Bus SDRAM machine Mode Register */
  VUWORD  memc_lsdmr;         /* Local Bus SDRAM machine Mode Register */
  VUBYTE  memc_purt;          /* PowerPC Bus assigned VUPM Refresh Timer */
  VUBYTE  reserved24[0x3];    /* Reserved area */
  VUBYTE  memc_psrt;          /* PowerPC Bus assigned SDRAM Refresh Timer */
  VUBYTE  reserved25[0x3];    /* Reserved area */
  VUBYTE  memc_lurt;          /* Local Bus assigned VUPM Refresh Timer */
  VUBYTE  reserved26[0x3];    /* Reserved area */
  VUBYTE  memc_lsrt;          /* Local Bus assigned SDRAM Refresh Timer */
  VUBYTE  reserved27[0x3];    /* Reserved area */
  VUWORD  memc_immr;          /* Internal Memory Map Register */

  /* pci */
  VUWORD  pcibr0;             /* Base address+valid for PCI window 1 */
  VUWORD  pcibr1;             /* Base address+valid for PCI window 2 */
  VUBYTE  reserved28[0x10];   /* Reserved area */
  VUWORD  pcimsk0;            /* Mask for PCI window 1 */
  VUWORD  pcimsk1;            /* Mask for PCI window 2 */
  VUBYTE  reserved29[0x54];   /* Reserved area */

  /* si_timers */