📄 scr8f0.h
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#include <stdio.h>
#include <conio.h>
#include <string.h>
#include <stdlib.h>
#include <math.h>
//#include "tun0297.h"
//#include "def.h"
#include "dos.h"
//papi i2c.h file
/* standard definition */
typedef unsigned char U8;
typedef unsigned long U32;
typedef char S8;
typedef long S32;
typedef unsigned int U16;
typedef int S16;
// papilon 2001.02.21
#define ROUTINE
#define PrnDataAddressBase 0x0378 // default value for the port address
#define READ 0
#define WRITE 1
#define FALSE 0
#define TRUE 1
#define LOW FALSE
#define HIGH TRUE
#define SDA 0x01
#define SDAHIGH 0x00
#define SDALOW 0x80
#define SCL 0x02
#define SCLHIGH 0x08
#define SCLLOW 0x00
#define ACK 0x04
//compil.h
//***********************************//
/*
List of the #defines used for insuring software portability .
*/
#define CHIPADDRESS 0x38
/*
//=============================//
// //
// DEFINITION OF THE HOST //
// //
//=============================//
*/
/********conditional compilation : PC OS codes ****************************/
/*
The values are splitted in two sets :
0 -> 999 reserved for micros
1000 -> 1999 reserved for PC OS
*/
#define ST20_SWC 100 /* for ST20 SWC tool set */
/**/
#define DOS 900 /* for windows 311 */
/********conditional compilation : languages ***************************/
#define C 1001
/****** choice of the host **********************************************/
#define HOST DOS
/****** choice of the language ******************************************/
#define LANGUAGE C
//def.h
/*********** I2C structure definition ***********************************/
typedef enum {OK = 0,NOACK,WRONGADR} PPSTATE;
/*********** Register structure definition ******************************/
typedef enum {NO = 0, YES = 1, AUTO = 2} FLAG ; /*version 3p8 */
/*********** Signal structure *************************************/
typedef struct
{
S32 Frequency ; /* carrier frequency (in Hz) */
U32 SymbolRate; /* Symbol Rate (in Baud) */
S32 QAMSize; /* QAM size (16/32/64/128/256) */
} SIGNAL;
/*********** Register structure *************************************/
typedef struct
{
U8 Addr, //Address
Reset, //Default value
Value, //Current value
Store; //Stored value
S8 Name[30]; //Name
} REGISTER;
typedef struct
{
S32 Reg; //Register index
U8 Pos, //Bit position
Bits, //Bit width
Type, //Signed or unsigned
Mask; //Mask compute with width and position
S8 Name[30]; //Name
} FIELD;
typedef S8 TITLE ;
#define FALSE 0
#define TRUE 1
/**/
#define NBPARAM 50
#define NBREG 86 // papi 86
#define NBFIELD 188
/**/
#define SET 0
#define GET 1
#define NOCHANGE 0
#define END 0
#define ON 1
#define OFF 0
#define UNSIGNED 0
#define SIGNED 1
#define QAM16 0
#define QAM32 1
#define QAM64 4
#define QAM128 2
#define QAM256 3
/* info */
/**/
/**/
/**/
/* MACRO d閒initions */
#define MAX(X,Y) ((X)>=(Y)) ? (X) : (Y)
#define MIN(X,Y) ((X)<=(Y)) ? (X) : (Y)
//reg0297.h
/******** GLOBAL VARIABLES ******************************************************************/
S32 NbI2CAccess; /* I2C Access counter (1 read or 1 write = 1 access) */
S32 I2cStatus; /* I2c status ; Bit format : ACK SCL SDA =b111=0x7 */
/* I2cStatus=0x07 : no fail */
/* I2cStatus=0x06 : SDA stuck to gnd */
/* I2cStatus=0x05 : SCL stuck to gnd */
/* I2cStatus=0x03 : no ACKNOWLEDGE from slave IC */
U32 I2cPPortAddress ; /* parallel port address */
U32 I2cSTVAddress ; /* Chip Address */
U32 I2cTunerAddress ; /* Tuner Address */
U32 prnDataAddress ; /* parallel Data address */
U32 prnStatusAddress ; /* parallel Status address */
U32 prnControlAddress ; /* parallel Control address */
S32 I2cTempoValue ; /* temporization for I2C slow slave IC */
/********************************************************************************************/
//map297.h
//
// REGISTERS
//
#define EQU_0 0
#define EQU_1 1
#define EQU_3 2
#define EQU_4 3
#define EQU_7 4
#define EQU_8 5
#define INITDEM_0 6
#define INITDEM_1 7
#define INITDEM_2 8
#define INITDEM_3 9
#define INITDEM_4 10
#define INITDEM_5 11
#define DELAGC_0 12
#define DELAGC_1 13
#define DELAGC_2 14
#define DELAGC_3 15
#define DELAGC_4 16
#define DELAGC_5 17
#define DELAGC_6 18
#define DELAGC_7 19
#define DELAGC_8 20
#define WBAGC_0 21
#define WBAGC_1 22
#define WBAGC_2 23
#define WBAGC_3 24
#define WBAGC_4 25
#define WBAGC_5 26
#define WBAGC_6 27
#define WBAGC_9 28
#define WBAGC_10 29
#define WBAGC_11 30
#define STLOOP_2 31
#define STLOOP_3 32
#define STLOOP_5 33
#define STLOOP_6 34
#define STLOOP_7 35
#define STLOOP_8 36
#define STLOOP_9 37
#define STLOOP_10 38
#define STLOOP_11 39
#define CRL_0 40
#define CRL_1 41
#define CRL_2 42
#define CRL_3 43
#define CRL_4 44
#define CRL_5 45
#define CRL_6 46
#define CRL_7 47
#define CRL_8 48
#define CRL_9 49
#define CRL_10 50
#define CRL_11 51
#define PMFAGC_0 52
#define PMFAGC_1 53
#define PMFAGC_2 54
#define PMFAGC_3 55
#define PMFAGC_4 56
#define CTRL_0 57
#define CTRL_1 58
#define CTRL_2 59
#define CTRL_3 60
#define CTRL_4 61
#define CTRL_5 62
#define CTRL_6 63
#define CTRL_7 64
#define CTRL_8 65
#define CTRL_9 66
#define DEINT_SYNC_0 67
#define DEINT_SYNC_1 68
#define BERT_0 69
#define BERT_1 70
#define BERT_2 71
#define DEINT_0 72
#define DEINT_1 73
#define OUTFORMAT_0 74
#define OUTFORMAT_1 75
#define OUTFORMAT_2 76
#define RS_DESC_0 77
#define RS_DESC_1 78
#define RS_DESC_2 79
#define RS_DESC_3 80
#define RS_DESC_4 81
#define RS_DESC_5 82
#define RS_DESC_14 83
#define RS_DESC_15 84
// Test registers
#define TST_EQU_2 85
#if 0
#define TST_EQU_5 86//papi
#define TST_EQU_6 87//papi
#endif
//
// FIELDS
//
#define U_THRESHOLD 0
#define MODE_SELECT 1
#define BLIND_U 2
#define INITIAL_U 3
#define EQ_FSM_CTL 4
#define EQ_COEFF_CTL 5
#define NBLIND 6
#define NOISE_EST_LO 7
#define NOISE_EST_HI 8
#define DEM_FQCY_LO 9
#define DEM_FQCY_HI 10
#define LATENCY 11
#define SCAN_STEP_LO 12
#define CHSCANITEN 13
#define CHSCANITSOFT 14
#define SCAN_STEP_HI 15
#define IN_DEMOD_EN 16
#define SCAN_ON 17
#define AUTOSTOP 18
#define SCALE_A 19
#define SCALE_B 20
#define AGC2MAX 21
#define AGC2MIN 22
#define AGC1MAX 23
#define AGC1MIN 24
#define RATIO_A 25
#define RATIO_B 26
#define RATIO_C 27
#define AGC2_THRES 28
#define DAGC_ON 29
#define FRZ2_CTRL 30
#define FRZ1_CTRL 31
#define TIME_CST 32
#define OVF_RATE_LO 33
#define CORNER_RATE_LO 34
#define OVF_RATE_HI 35
#define CORNER_RATE_HI 36
#define I_REF 37
#define AGC2SD_LO 38
#define AGC2SD_HI 39
#define ACQ_THRESH 40
#define WAGC_CLR 41
#define WAGC_INV 42
#define WAGC_EN 43
#define WAGC_ACQ 44
#define SWAP 45
#define ROLL_LO 46
#define ACQ_COUNT_LO 47
#define ACQ_COUNT_HI 48
#define ROLL_HI 49
#define IF_PWM_LO 50
#define TARGET_RATE_LO 51
#define IF_PWM_HI 52
#define TARGET_RATE_HI 53
#define GAIN_SCALE_PATH0 54
#define GAIN_SCALE_PATH1 55
#define INTEGRAL_GAIN_HI 56
#define DIRECT_GAIN_LO 57
#define SYMB_RATE_0 58
#define SYMB_RATE_1 59
#define SYMB_RATE_2 60
#define SYMB_RATE_3 61
#define INTEGRAL_GAIN_LO 62
#define DIRECT_GAIN_HI 63
#define PHASE_EN 64
#define PHASE_CLR 65
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