📄 adc.lst
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00000170 E5100000 LDR R0,=0x3FF
00000174 E0011000 AND R1,R1,R0
00000178 E5100000 LDR R0,=ADC1Value + 0x4 ; ADC1Value+4
0000017C E5801000 STR R1,[R0,#0x0] ; ADC1Value+4
179: break;
00000180 EA00002E B L_37 ; Targ=0x240
180: case 0x04:
00000184 L_41:
181: ADC1Value[2] = ( AD1DR2 >> 6 ) & 0x3FF;
00000184 E5100000 LDR R0,=0xE0060018
00000188 E5901000 LDR R1,[R0,#0x0]
0000018C E1A01321 MOV R1,R1,LSR #6
00000190 E5100000 LDR R0,=0x3FF
00000194 E0011000 AND R1,R1,R0
00000198 E5100000 LDR R0,=ADC1Value + 0x8 ; ADC1Value+8
0000019C E5801000 STR R1,[R0,#0x0] ; ADC1Value+8
182: break;
000001A0 EA000026 B L_37 ; Targ=0x240
183: case 0x08:
000001A4 L_42:
184: ADC1Value[3] = ( AD1DR3 >> 6 ) & 0x3FF;
000001A4 E5100000 LDR R0,=0xE006001C
000001A8 E5901000 LDR R1,[R0,#0x0]
000001AC E1A01321 MOV R1,R1,LSR #6
000001B0 E5100000 LDR R0,=0x3FF
000001B4 E0011000 AND R1,R1,R0
000001B8 E5100000 LDR R0,=ADC1Value + 0xC ; ADC1Value+12
000001BC E5801000 STR R1,[R0,#0x0] ; ADC1Value+12
ARM COMPILER V2.53, adc 12/10/06 20:06:10 PAGE 14
185: break;
000001C0 EA00001E B L_37 ; Targ=0x240
186: case 0x10:
000001C4 L_43:
187: ADC1Value[4] = ( AD1DR4 >> 6 ) & 0x3FF;
000001C4 E5100000 LDR R0,=0xE0060020
000001C8 E5901000 LDR R1,[R0,#0x0]
000001CC E1A01321 MOV R1,R1,LSR #6
000001D0 E5100000 LDR R0,=0x3FF
000001D4 E0011000 AND R1,R1,R0
000001D8 E5100000 LDR R0,=ADC1Value + 0x10 ; ADC1Value+16
000001DC E5801000 STR R1,[R0,#0x0] ; ADC1Value+16
188: break;
000001E0 EA000016 B L_37 ; Targ=0x240
189: case 0x20:
000001E4 L_44:
190: ADC1Value[5] = ( AD1DR5 >> 6 ) & 0x3FF;
000001E4 E5100000 LDR R0,=0xE0060024
000001E8 E5901000 LDR R1,[R0,#0x0]
000001EC E1A01321 MOV R1,R1,LSR #6
000001F0 E5100000 LDR R0,=0x3FF
000001F4 E0011000 AND R1,R1,R0
000001F8 E5100000 LDR R0,=ADC1Value + 0x14 ; ADC1Value+20
000001FC E5801000 STR R1,[R0,#0x0] ; ADC1Value+20
191: break;
00000200 EA00000E B L_37 ; Targ=0x240
192: case 0x40:
00000204 L_45:
193: ADC1Value[6] = ( AD1DR6 >> 6 ) & 0x3FF;
00000204 E5100000 LDR R0,=0xE0060028
00000208 E5901000 LDR R1,[R0,#0x0]
0000020C E1A01321 MOV R1,R1,LSR #6
00000210 E5100000 LDR R0,=0x3FF
00000214 E0011000 AND R1,R1,R0
00000218 E5100000 LDR R0,=ADC1Value + 0x18 ; ADC1Value+24
0000021C E5801000 STR R1,[R0,#0x0] ; ADC1Value+24
194: break;
00000220 EA000006 B L_37 ; Targ=0x240
195: case 0x80:
00000224 L_46:
196: ADC1Value[7] = ( AD1DR7 >> 6 ) & 0x3FF;
00000224 E5100000 LDR R0,=0xE006002C
00000228 E5901000 LDR R1,[R0,#0x0]
0000022C E1A01321 MOV R1,R1,LSR #6
00000230 E5100000 LDR R0,=0x3FF
00000234 E0011000 AND R1,R1,R0
00000238 E5100000 LDR R0,=ADC1Value + 0x1C ; ADC1Value+28
0000023C E5801000 STR R1,[R0,#0x0] ; ADC1Value+28
200: }
00000240 L_37:
201: AD1CR &= 0xF8FFFFFF; /* stop ADC now */
00000240 E5100000 LDR R0,=0xE0060000
00000244 E5901000 LDR R1,[R0,#0x0]
00000248 E3C11407 BIC R1,R1,#0x7000000
0000024C E5801000 STR R1,[R0,#0x0]
202: ADC1IntDone = 1;
00000250 E3A01001 MOV R1,#0x1
00000254 E5100000 LDR R0,=ADC1IntDone ; ADC1IntDone
00000258 E5801000 STR R1,[R0,#0x0] ; ADC1IntDone
203: }
0000025C L_36:
205: IDISABLE;
0000025C E8BD4000 LDMFD R13!,{LR}
00000260 E321F092 MSR CPSR_c,#0x92
00000264 E8BD4000 LDMFD R13!,{LR}
00000268 E16FF00E MSR SPSR_cxsf,R14
ARM COMPILER V2.53, adc 12/10/06 20:06:10 PAGE 15
206: VICVectAddr = 0; /* Acknowledge Interrupt */
0000026C E3A01000 MOV R1,#0x0
00000270 E5100000 LDR R0,=0xFFFFF030
00000274 E5801000 STR R1,[R0,#0x0]
00000278 ; SCOPE-END
207: }
00000278 L_35:
00000278 E8BD4007 LDMIA R13!,{R0-R2,LR}
0000027C E25EF004 SUBS R15,R14,#0x0004
00000280 ENDP ; 'ADC1Handler?A'
*** CODE SEGMENT '?PR?ADCInit?T?adc':
219: DWORD ADCInit( DWORD ADC_Clk )
00000000 B510 PUSH {R4,LR}
00000002 1C04 MOV R4,R0 ; ADC_Clk
00000004 ---- Variable 'ADC_Clk' assigned to Register 'R4' ----
222: PINSEL0 = 0x0F333F00;
00000004 4800 LDR R1,=0xF333F00
00000006 4800 LDR R0,=0xE002C000
00000008 6001 STR R1,[R0,#0x0]
223: PINSEL1 = 0x15541800;
0000000A 4800 LDR R1,=0x15541800
0000000C 4800 LDR R0,=0xE002C004
0000000E 6001 STR R1,[R0,#0x0]
225: AD0CR = ( 0x01 << 0 ) | // SEL=1,select channel 0, 1 to 4 on ADC0
00000010 1C21 MOV R1,R4 ; ADC_Clk
00000012 4800 LDR R0,=0xE4E1C0
00000014 F7FF BL ?C?UDIV?T ; T=0x0001 (1) ; ?C?UDIV?T
00000016 FFF4 BL ?C?UDIV?T ; T=0x0001 (2) ; ?C?UDIV?T
00000018 1C08 MOV R0,R1
0000001A 3901 SUB R1,#0x1
0000001C 0209 LSL R1,R1,#0x8
0000001E 4800 LDR R0,=0x200001
00000020 1C0B MOV R3,R1
00000022 4303 ORR R3,R0
00000024 4800 LDR R2,=0xE0034000
00000026 6013 STR R3,[R2,#0x0]
234: AD1CR = ( 0x01 << 0 ) | // SEL=1,select channel 0, 0 to 7 on ADC1
00000028 4301 ORR R1,R0
0000002A 4800 LDR R0,=0xE0060000
0000002C 6001 STR R1,[R0,#0x0]
246: AD0INTEN = 0x11E; // Enable all interrupts
0000002E 4800 LDR R1,=0x11E
00000030 4800 LDR R0,=0xE003400C
00000032 6001 STR R1,[R0,#0x0]
247: AD1INTEN = 0x1FF;
00000034 4800 LDR R1,=0x1FF
00000036 4800 LDR R0,=0xE006000C
00000038 6001 STR R1,[R0,#0x0]
249: if ( install_irq( ADC0_INT, (void *)ADC0Handler ) == FALSE )
0000003A 4900 LDR R1,=ADC0Handler?A ; ADC0Handler?A
0000003C 2012 MOV R0,#0x12
0000003E F7FF BL install_irq?T ; T=0x0001 (1)
00000040 FFDF BL install_irq?T ; T=0x0001 (2)
00000042 2800 CMP R0,#0x0 ; install_irq?T
00000044 D101 BNE L_47 ; T=0x0000004A
251: return (FALSE);
00000046 2000 MOV R0,#0x0
00000048 E008 B L_48 ; T=0x0000005C
252: }
0000004A L_47:
253: if ( install_irq( ADC1_INT, (void *)ADC1Handler ) == FALSE )
0000004A 4900 LDR R1,=ADC1Handler?A ; ADC1Handler?A
0000004C 2015 MOV R0,#0x15
0000004E F7FF BL install_irq?T ; T=0x0001 (1)
00000050 FFD7 BL install_irq?T ; T=0x0001 (2)
00000052 2800 CMP R0,#0x0 ; install_irq?T
ARM COMPILER V2.53, adc 12/10/06 20:06:10 PAGE 16
00000054 D101 BNE L_49 ; T=0x0000005A
255: return (FALSE);
00000056 2000 MOV R0,#0x0
00000058 E000 B L_48 ; T=0x0000005C
256: }
0000005A L_49:
259: return (TRUE);
0000005A 2001 MOV R0,#0x1
260: }
0000005C L_48:
0000005C BC10 POP {R4}
0000005E BC08 POP {R3}
00000060 4718 BX R3
00000062 ENDP ; 'ADCInit?T'
*** CODE SEGMENT '?PR?ADC0Read?T?adc':
271: DWORD ADC0Read( BYTE channelNum )
00000000 1C01 MOV R1,R0 ; channelNum
00000002 ---- Variable 'channelNum' assigned to Register 'R1' ----
278: if ( channelNum >= ADC_NUM )
00000002 1C08 MOV R0,R1 ; channelNum
00000004 0600 LSL R0,R0,#0x18 ; channelNum
00000006 0E00 LSR R0,R0,#0x18
00000008 2808 CMP R0,#0x8
0000000A DB00 BLT L_50 ; T=0x0000000E
280: channelNum = 0; /* reset channel number to 0 */
0000000C 2100 MOV R1,#0x0
281: }
0000000E L_50:
282: AD0CR &= 0xFFFFFF00;
0000000E 23FF MOV R3,#0xFF
00000010 4800 LDR R0,=0xE0034000
00000012 6802 LDR R2,[R0,#0x0]
00000014 439A BIC R2,R3
00000016 6002 STR R2,[R0,#0x0]
283: AD0CR |= (1 << 24) | (1 << channelNum);
00000018 1C08 MOV R0,R1 ; channelNum
0000001A 0600 LSL R0,R0,#0x18 ; channelNum
0000001C 0E00 LSR R0,R0,#0x18
0000001E 2301 MOV R3,#0x1
00000020 4083 LSL R3,R0
00000022 4800 LDR R0,=0x1000000
00000024 4303 ORR R3,R0
00000026 4800 LDR R0,=0xE0034000
00000028 6802 LDR R2,[R0,#0x0]
0000002A 431A ORR R2,R3
0000002C 6002 STR R2,[R0,#0x0]
306: return ( channelNum ); /* if it's interrupt driven, the
0000002E 1C08 MOV R0,R1 ; channelNum
00000030 0600 LSL R0,R0,#0x18 ; channelNum
00000032 0E00 LSR R0,R0,#0x18
310: }
00000034 4770 BX R14
00000036 ENDP ; 'ADC0Read?T'
*** CODE SEGMENT '?PR?ADC1Read?T?adc':
321: DWORD ADC1Read( BYTE channelNum )
00000000 1C01 MOV R1,R0 ; channelNum
00000002 ---- Variable 'channelNum' assigned to Register 'R1' ----
328: if ( channelNum >= ADC_NUM )
00000002 1C08 MOV R0,R1 ; channelNum
00000004 0600 LSL R0,R0,#0x18 ; channelNum
00000006 0E00 LSR R0,R0,#0x18
00000008 2808 CMP R0,#0x8
0000000A DB00 BLT L_52 ; T=0x0000000E
330: channelNum = 0; /* reset channel number to 0 */
0000000C 2100 MOV R1,#0x0
331: }
ARM COMPILER V2.53, adc 12/10/06 20:06:10 PAGE 17
0000000E L_52:
332: AD1CR &= 0xFFFFFF00;
0000000E 23FF MOV R3,#0xFF
00000010 4800 LDR R0,=0xE0060000
00000012 6802 LDR R2,[R0,#0x0]
00000014 439A BIC R2,R3
00000016 6002 STR R2,[R0,#0x0]
333: AD1CR |= (1 << 24) | (1 << channelNum);
00000018 1C08 MOV R0,R1 ; channelNum
0000001A 0600 LSL R0,R0,#0x18 ; channelNum
0000001C 0E00 LSR R0,R0,#0x18
0000001E 2301 MOV R3,#0x1
00000020 4083 LSL R3,R0
00000022 4800 LDR R0,=0x1000000
00000024 4303 ORR R3,R0
00000026 4800 LDR R0,=0xE0060000
00000028 6802 LDR R2,[R0,#0x0]
0000002A 431A ORR R2,R3
0000002C 6002 STR R2,[R0,#0x0]
357: return ( channelNum );
0000002E 1C08 MOV R0,R1 ; channelNum
00000030 0600 LSL R0,R0,#0x18 ; channelNum
00000032 0E00 LSR R0,R0,#0x18
359: }
00000034 4770 BX R14
00000036 ENDP ; 'ADC1Read?T'
Module Information Static
----------------------------------
code size = ------
data size = 72
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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